Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
1 // SPDX-License-Identifier: GPL-2.0
72 /* PCIe V2 per-port registers */
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
143 * struct mtk_pcie_soc - differentiate between host generations
161 * struct mtk_pcie_port - PCIe port information
205 * struct mtk_pcie - PCIe host information
208 * @free_ck: free-run reference clock
209 * @mem: non-prefetchable memory resource
211 * @soc: pointer to SoC-dependent operations
224 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerdown()
226 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_subsys_powerdown()
234 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_port_free()
235 struct device *dev = pcie->dev; in mtk_pcie_port_free()
237 devm_iounmap(dev, port->base); in mtk_pcie_port_free()
238 list_del(&port->list); in mtk_pcie_port_free()
246 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_put_resources()
247 phy_power_off(port->phy); in mtk_pcie_put_resources()
248 phy_exit(port->phy); in mtk_pcie_put_resources()
249 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_put_resources()
250 clk_disable_unprepare(port->obff_ck); in mtk_pcie_put_resources()
251 clk_disable_unprepare(port->axi_ck); in mtk_pcie_put_resources()
252 clk_disable_unprepare(port->aux_ck); in mtk_pcie_put_resources()
253 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_put_resources()
254 clk_disable_unprepare(port->sys_ck); in mtk_pcie_put_resources()
266 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, in mtk_pcie_check_cfg_cpld()
272 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) in mtk_pcie_check_cfg_cpld()
285 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_rd_cfg()
286 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_rd_cfg()
288 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_rd_cfg()
291 tmp = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
293 writel(tmp, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
300 *val = readl(port->base + PCIE_CFG_RDATA); in mtk_pcie_hw_rd_cfg()
315 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_wr_cfg()
316 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_wr_cfg()
318 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_wr_cfg()
322 writel(val, port->base + PCIE_CFG_WDATA); in mtk_pcie_hw_wr_cfg()
325 val = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
327 writel(val, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
336 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_find_port()
344 while (bus && bus->number) { in mtk_pcie_find_port()
345 dev = bus->self; in mtk_pcie_find_port()
346 bus = dev->bus; in mtk_pcie_find_port()
347 devfn = dev->devfn; in mtk_pcie_find_port()
350 list_for_each_entry(port, &pcie->ports, list) in mtk_pcie_find_port()
351 if (port->slot == PCI_SLOT(devfn)) in mtk_pcie_find_port()
361 u32 bn = bus->number; in mtk_pcie_config_read()
381 u32 bn = bus->number; in mtk_pcie_config_write()
400 /* MT2712/MT7622 only support 32-bit MSI addresses */ in mtk_compose_msi_msg()
401 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_compose_msi_msg()
402 msg->address_hi = 0; in mtk_compose_msi_msg()
403 msg->address_lo = lower_32_bits(addr); in mtk_compose_msi_msg()
405 msg->data = data->hwirq; in mtk_compose_msi_msg()
407 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", in mtk_compose_msi_msg()
408 (int)data->hwirq, msg->address_hi, msg->address_lo); in mtk_compose_msi_msg()
414 return -EINVAL; in mtk_msi_set_affinity()
420 u32 hwirq = data->hwirq; in mtk_msi_ack_irq()
422 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); in mtk_msi_ack_irq()
435 struct mtk_pcie_port *port = domain->host_data; in mtk_pcie_irq_domain_alloc()
439 mutex_lock(&port->lock); in mtk_pcie_irq_domain_alloc()
441 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); in mtk_pcie_irq_domain_alloc()
443 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
444 return -ENOSPC; in mtk_pcie_irq_domain_alloc()
447 __set_bit(bit, port->msi_irq_in_use); in mtk_pcie_irq_domain_alloc()
449 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
452 domain->host_data, handle_edge_irq, in mtk_pcie_irq_domain_alloc()
464 mutex_lock(&port->lock); in mtk_pcie_irq_domain_free()
466 if (!test_bit(d->hwirq, port->msi_irq_in_use)) in mtk_pcie_irq_domain_free()
467 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", in mtk_pcie_irq_domain_free()
468 d->hwirq); in mtk_pcie_irq_domain_free()
470 __clear_bit(d->hwirq, port->msi_irq_in_use); in mtk_pcie_irq_domain_free()
472 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_free()
497 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); in mtk_pcie_allocate_msi_domains()
499 mutex_init(&port->lock); in mtk_pcie_allocate_msi_domains()
501 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, in mtk_pcie_allocate_msi_domains()
503 if (!port->inner_domain) { in mtk_pcie_allocate_msi_domains()
504 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); in mtk_pcie_allocate_msi_domains()
505 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
508 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, in mtk_pcie_allocate_msi_domains()
509 port->inner_domain); in mtk_pcie_allocate_msi_domains()
510 if (!port->msi_domain) { in mtk_pcie_allocate_msi_domains()
511 dev_err(port->pcie->dev, "failed to create MSI domain\n"); in mtk_pcie_allocate_msi_domains()
512 irq_domain_remove(port->inner_domain); in mtk_pcie_allocate_msi_domains()
513 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
524 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_pcie_enable_msi()
526 writel(val, port->base + PCIE_IMSI_ADDR); in mtk_pcie_enable_msi()
528 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
530 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
537 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_irq_teardown()
538 irq_set_chained_handler_and_data(port->irq, NULL, NULL); in mtk_pcie_irq_teardown()
540 if (port->irq_domain) in mtk_pcie_irq_teardown()
541 irq_domain_remove(port->irq_domain); in mtk_pcie_irq_teardown()
544 if (port->msi_domain) in mtk_pcie_irq_teardown()
545 irq_domain_remove(port->msi_domain); in mtk_pcie_irq_teardown()
546 if (port->inner_domain) in mtk_pcie_irq_teardown()
547 irq_domain_remove(port->inner_domain); in mtk_pcie_irq_teardown()
550 irq_dispose_mapping(port->irq); in mtk_pcie_irq_teardown()
558 irq_set_chip_data(irq, domain->host_data); in mtk_pcie_intx_map()
570 struct device *dev = port->pcie->dev; in mtk_pcie_init_irq_domain()
577 dev_err(dev, "no PCIe Intc node found\n"); in mtk_pcie_init_irq_domain()
578 return -ENODEV; in mtk_pcie_init_irq_domain()
581 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, in mtk_pcie_init_irq_domain()
584 if (!port->irq_domain) { in mtk_pcie_init_irq_domain()
586 return -ENODEV; in mtk_pcie_init_irq_domain()
608 status = readl(port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
612 writel(1 << bit, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
613 virq = irq_find_mapping(port->irq_domain, in mtk_pcie_intr_handler()
614 bit - INTX_SHIFT); in mtk_pcie_intr_handler()
623 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { in mtk_pcie_intr_handler()
625 virq = irq_find_mapping(port->inner_domain, bit); in mtk_pcie_intr_handler()
630 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
640 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_setup_irq()
641 struct device *dev = pcie->dev; in mtk_pcie_setup_irq()
651 port->irq = platform_get_irq(pdev, port->slot); in mtk_pcie_setup_irq()
652 if (port->irq < 0) in mtk_pcie_setup_irq()
653 return port->irq; in mtk_pcie_setup_irq()
655 irq_set_chained_handler_and_data(port->irq, in mtk_pcie_setup_irq()
663 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port_v2()
667 const struct mtk_pcie_soc *soc = port->pcie->soc; in mtk_pcie_startup_port_v2()
671 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); in mtk_pcie_startup_port_v2()
673 mem = entry->res; in mtk_pcie_startup_port_v2()
675 return -EINVAL; in mtk_pcie_startup_port_v2()
677 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ in mtk_pcie_startup_port_v2()
678 if (pcie->base) { in mtk_pcie_startup_port_v2()
679 val = readl(pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
680 val |= PCIE_CSR_LTSSM_EN(port->slot) | in mtk_pcie_startup_port_v2()
681 PCIE_CSR_ASPM_L1_EN(port->slot); in mtk_pcie_startup_port_v2()
682 writel(val, pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
686 writel(0, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
693 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
695 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ in mtk_pcie_startup_port_v2()
696 val = readl(port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
699 writel(val, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
702 if (soc->need_fix_class_id) { in mtk_pcie_startup_port_v2()
704 writew(val, port->base + PCIE_CONF_VEND_ID); in mtk_pcie_startup_port_v2()
707 writew(val, port->base + PCIE_CONF_CLASS_ID); in mtk_pcie_startup_port_v2()
710 if (soc->need_fix_device_id) in mtk_pcie_startup_port_v2()
711 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); in mtk_pcie_startup_port_v2()
714 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, in mtk_pcie_startup_port_v2()
718 return -ETIMEDOUT; in mtk_pcie_startup_port_v2()
721 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
723 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
729 val = lower_32_bits(mem->start) | in mtk_pcie_startup_port_v2()
731 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); in mtk_pcie_startup_port_v2()
733 val = upper_32_bits(mem->start); in mtk_pcie_startup_port_v2()
734 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); in mtk_pcie_startup_port_v2()
738 writel(val, port->base + PCIE_AXI_WINDOW0); in mtk_pcie_startup_port_v2()
746 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus()
749 bus->number), pcie->base + PCIE_CFG_ADDR); in mtk_pcie_map_bus()
751 return pcie->base + PCIE_CFG_DATA + (where & 3); in mtk_pcie_map_bus()
762 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port()
763 u32 func = PCI_FUNC(port->slot << 3); in mtk_pcie_startup_port()
764 u32 slot = PCI_SLOT(port->slot << 3); in mtk_pcie_startup_port()
769 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
770 val |= PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
771 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
773 /* de-assert port PERST_N */ in mtk_pcie_startup_port()
774 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
775 val &= ~PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
776 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
779 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, in mtk_pcie_startup_port()
783 return -ETIMEDOUT; in mtk_pcie_startup_port()
786 val = readl(pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
787 val |= PCIE_PORT_INT_EN(port->slot); in mtk_pcie_startup_port()
788 writel(val, pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
792 port->base + PCIE_BAR0_SETUP); in mtk_pcie_startup_port()
795 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); in mtk_pcie_startup_port()
799 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
800 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
804 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
805 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
807 /* configure RC FTS number to 250 when it leaves L0s */ in mtk_pcie_startup_port()
809 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
810 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
814 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
815 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
822 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_enable_port()
823 struct device *dev = pcie->dev; in mtk_pcie_enable_port()
826 err = clk_prepare_enable(port->sys_ck); in mtk_pcie_enable_port()
828 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); in mtk_pcie_enable_port()
832 err = clk_prepare_enable(port->ahb_ck); in mtk_pcie_enable_port()
834 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); in mtk_pcie_enable_port()
838 err = clk_prepare_enable(port->aux_ck); in mtk_pcie_enable_port()
840 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); in mtk_pcie_enable_port()
844 err = clk_prepare_enable(port->axi_ck); in mtk_pcie_enable_port()
846 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); in mtk_pcie_enable_port()
850 err = clk_prepare_enable(port->obff_ck); in mtk_pcie_enable_port()
852 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); in mtk_pcie_enable_port()
856 err = clk_prepare_enable(port->pipe_ck); in mtk_pcie_enable_port()
858 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); in mtk_pcie_enable_port()
862 reset_control_assert(port->reset); in mtk_pcie_enable_port()
863 reset_control_deassert(port->reset); in mtk_pcie_enable_port()
865 err = phy_init(port->phy); in mtk_pcie_enable_port()
867 dev_err(dev, "failed to initialize port%d phy\n", port->slot); in mtk_pcie_enable_port()
871 err = phy_power_on(port->phy); in mtk_pcie_enable_port()
873 dev_err(dev, "failed to power on port%d phy\n", port->slot); in mtk_pcie_enable_port()
877 if (!pcie->soc->startup(port)) in mtk_pcie_enable_port()
880 dev_info(dev, "Port%d link down\n", port->slot); in mtk_pcie_enable_port()
882 phy_power_off(port->phy); in mtk_pcie_enable_port()
884 phy_exit(port->phy); in mtk_pcie_enable_port()
886 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_enable_port()
888 clk_disable_unprepare(port->obff_ck); in mtk_pcie_enable_port()
890 clk_disable_unprepare(port->axi_ck); in mtk_pcie_enable_port()
892 clk_disable_unprepare(port->aux_ck); in mtk_pcie_enable_port()
894 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_enable_port()
896 clk_disable_unprepare(port->sys_ck); in mtk_pcie_enable_port()
906 struct device *dev = pcie->dev; in mtk_pcie_parse_port()
913 return -ENOMEM; in mtk_pcie_parse_port()
916 port->base = devm_platform_ioremap_resource_byname(pdev, name); in mtk_pcie_parse_port()
917 if (IS_ERR(port->base)) { in mtk_pcie_parse_port()
919 return PTR_ERR(port->base); in mtk_pcie_parse_port()
923 port->sys_ck = devm_clk_get(dev, name); in mtk_pcie_parse_port()
924 if (IS_ERR(port->sys_ck)) { in mtk_pcie_parse_port()
926 return PTR_ERR(port->sys_ck); in mtk_pcie_parse_port()
931 port->ahb_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
932 if (IS_ERR(port->ahb_ck)) in mtk_pcie_parse_port()
933 return PTR_ERR(port->ahb_ck); in mtk_pcie_parse_port()
936 port->axi_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
937 if (IS_ERR(port->axi_ck)) in mtk_pcie_parse_port()
938 return PTR_ERR(port->axi_ck); in mtk_pcie_parse_port()
941 port->aux_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
942 if (IS_ERR(port->aux_ck)) in mtk_pcie_parse_port()
943 return PTR_ERR(port->aux_ck); in mtk_pcie_parse_port()
946 port->obff_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
947 if (IS_ERR(port->obff_ck)) in mtk_pcie_parse_port()
948 return PTR_ERR(port->obff_ck); in mtk_pcie_parse_port()
951 port->pipe_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
952 if (IS_ERR(port->pipe_ck)) in mtk_pcie_parse_port()
953 return PTR_ERR(port->pipe_ck); in mtk_pcie_parse_port()
955 snprintf(name, sizeof(name), "pcie-rst%d", slot); in mtk_pcie_parse_port()
956 port->reset = devm_reset_control_get_optional_exclusive(dev, name); in mtk_pcie_parse_port()
957 if (PTR_ERR(port->reset) == -EPROBE_DEFER) in mtk_pcie_parse_port()
958 return PTR_ERR(port->reset); in mtk_pcie_parse_port()
961 snprintf(name, sizeof(name), "pcie-phy%d", slot); in mtk_pcie_parse_port()
962 port->phy = devm_phy_optional_get(dev, name); in mtk_pcie_parse_port()
963 if (IS_ERR(port->phy)) in mtk_pcie_parse_port()
964 return PTR_ERR(port->phy); in mtk_pcie_parse_port()
966 port->slot = slot; in mtk_pcie_parse_port()
967 port->pcie = pcie; in mtk_pcie_parse_port()
969 if (pcie->soc->setup_irq) { in mtk_pcie_parse_port()
970 err = pcie->soc->setup_irq(port, node); in mtk_pcie_parse_port()
975 INIT_LIST_HEAD(&port->list); in mtk_pcie_parse_port()
976 list_add_tail(&port->list, &pcie->ports); in mtk_pcie_parse_port()
983 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerup()
991 pcie->base = devm_ioremap_resource(dev, regs); in mtk_pcie_subsys_powerup()
992 if (IS_ERR(pcie->base)) { in mtk_pcie_subsys_powerup()
994 return PTR_ERR(pcie->base); in mtk_pcie_subsys_powerup()
998 pcie->free_ck = devm_clk_get(dev, "free_ck"); in mtk_pcie_subsys_powerup()
999 if (IS_ERR(pcie->free_ck)) { in mtk_pcie_subsys_powerup()
1000 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) in mtk_pcie_subsys_powerup()
1001 return -EPROBE_DEFER; in mtk_pcie_subsys_powerup()
1003 pcie->free_ck = NULL; in mtk_pcie_subsys_powerup()
1010 err = clk_prepare_enable(pcie->free_ck); in mtk_pcie_subsys_powerup()
1027 struct device *dev = pcie->dev; in mtk_pcie_setup()
1028 struct device_node *node = dev->of_node, *child; in mtk_pcie_setup()
1053 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_setup()
1057 if (list_empty(&pcie->ports)) in mtk_pcie_setup()
1068 struct device *dev = &pdev->dev; in mtk_pcie_probe()
1075 return -ENOMEM; in mtk_pcie_probe()
1079 pcie->dev = dev; in mtk_pcie_probe()
1080 pcie->soc = of_device_get_match_data(dev); in mtk_pcie_probe()
1082 INIT_LIST_HEAD(&pcie->ports); in mtk_pcie_probe()
1088 host->ops = pcie->soc->ops; in mtk_pcie_probe()
1089 host->sysdata = pcie; in mtk_pcie_probe()
1098 if (!list_empty(&pcie->ports)) in mtk_pcie_probe()
1108 struct list_head *windows = &host->windows; in mtk_pcie_free_resources()
1118 pci_stop_root_bus(host->bus); in mtk_pcie_remove()
1119 pci_remove_root_bus(host->bus); in mtk_pcie_remove()
1134 if (list_empty(&pcie->ports)) in mtk_pcie_suspend_noirq()
1137 list_for_each_entry(port, &pcie->ports, list) { in mtk_pcie_suspend_noirq()
1138 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_suspend_noirq()
1139 clk_disable_unprepare(port->obff_ck); in mtk_pcie_suspend_noirq()
1140 clk_disable_unprepare(port->axi_ck); in mtk_pcie_suspend_noirq()
1141 clk_disable_unprepare(port->aux_ck); in mtk_pcie_suspend_noirq()
1142 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_suspend_noirq()
1143 clk_disable_unprepare(port->sys_ck); in mtk_pcie_suspend_noirq()
1144 phy_power_off(port->phy); in mtk_pcie_suspend_noirq()
1145 phy_exit(port->phy); in mtk_pcie_suspend_noirq()
1148 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_suspend_noirq()
1158 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1161 clk_prepare_enable(pcie->free_ck); in mtk_pcie_resume_noirq()
1163 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_resume_noirq()
1167 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1168 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_resume_noirq()
1206 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1207 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1208 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1209 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1210 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1218 .name = "mtk-pcie",