Lines Matching full:bridge
8 * PCI bridge when the HW doesn't provide such a root port PCI
9 * bridge.
11 * It emulates a PCI bridge by providing a fake PCI configuration
21 #include "pci-bridge-emul.h"
72 * bridge that is not capable of a burst transfer of more than
78 * BIST register: implemented as read-only, as "A bridge that
153 * are RO, and bridge control (31:16) are a mix of RW, RO,
277 * bridge configuration space. The caller needs to have initialized
282 int pci_bridge_emul_init(struct pci_bridge_emul *bridge, in pci_bridge_emul_init() argument
285 BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END); in pci_bridge_emul_init()
287 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16); in pci_bridge_emul_init()
288 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; in pci_bridge_emul_init()
289 bridge->conf.cache_line_size = 0x10; in pci_bridge_emul_init()
290 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); in pci_bridge_emul_init()
291 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, in pci_bridge_emul_init()
294 if (!bridge->pci_regs_behavior) in pci_bridge_emul_init()
297 if (bridge->has_pcie) { in pci_bridge_emul_init()
298 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; in pci_bridge_emul_init()
299 bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST); in pci_bridge_emul_init()
300 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; in pci_bridge_emul_init()
301 bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); in pci_bridge_emul_init()
302 bridge->pcie_cap_regs_behavior = in pci_bridge_emul_init()
306 if (!bridge->pcie_cap_regs_behavior) { in pci_bridge_emul_init()
307 kfree(bridge->pci_regs_behavior); in pci_bridge_emul_init()
311 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &= in pci_bridge_emul_init()
313 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &= in pci_bridge_emul_init()
319 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &= in pci_bridge_emul_init()
321 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &= in pci_bridge_emul_init()
324 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= in pci_bridge_emul_init()
327 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &= in pci_bridge_emul_init()
329 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &= in pci_bridge_emul_init()
334 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; in pci_bridge_emul_init()
335 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; in pci_bridge_emul_init()
346 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge) in pci_bridge_emul_cleanup() argument
348 if (bridge->has_pcie) in pci_bridge_emul_cleanup()
349 kfree(bridge->pcie_cap_regs_behavior); in pci_bridge_emul_cleanup()
350 kfree(bridge->pci_regs_behavior); in pci_bridge_emul_cleanup()
356 * configuration space of the fake bridge. It will call back the
359 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, in pci_bridge_emul_conf_read() argument
364 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge, in pci_bridge_emul_conf_read()
369 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { in pci_bridge_emul_conf_read()
374 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { in pci_bridge_emul_conf_read()
379 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { in pci_bridge_emul_conf_read()
381 read_op = bridge->ops->read_pcie; in pci_bridge_emul_conf_read()
382 cfgspace = (__le32 *) &bridge->pcie_conf; in pci_bridge_emul_conf_read()
383 behavior = bridge->pcie_cap_regs_behavior; in pci_bridge_emul_conf_read()
385 read_op = bridge->ops->read_base; in pci_bridge_emul_conf_read()
386 cfgspace = (__le32 *) &bridge->conf; in pci_bridge_emul_conf_read()
387 behavior = bridge->pci_regs_behavior; in pci_bridge_emul_conf_read()
391 ret = read_op(bridge, reg, value); in pci_bridge_emul_conf_read()
418 * configuration space of the fake bridge. It will call back the
421 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, in pci_bridge_emul_conf_write() argument
426 void (*write_op)(struct pci_bridge_emul *bridge, int reg, in pci_bridge_emul_conf_write()
431 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) in pci_bridge_emul_conf_write()
434 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) in pci_bridge_emul_conf_write()
448 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); in pci_bridge_emul_conf_write()
452 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { in pci_bridge_emul_conf_write()
454 write_op = bridge->ops->write_pcie; in pci_bridge_emul_conf_write()
455 cfgspace = (__le32 *) &bridge->pcie_conf; in pci_bridge_emul_conf_write()
456 behavior = bridge->pcie_cap_regs_behavior; in pci_bridge_emul_conf_write()
458 write_op = bridge->ops->write_base; in pci_bridge_emul_conf_write()
459 cfgspace = (__le32 *) &bridge->conf; in pci_bridge_emul_conf_write()
460 behavior = bridge->pci_regs_behavior; in pci_bridge_emul_conf_write()
488 write_op(bridge, reg, old, new, mask); in pci_bridge_emul_conf_write()