57 /* DTMs live in the PMU space of XP registers */
200 		/* XP */
421 /* Good thing there are only 3 fundamental XP events... */
504 	/* We treat watchpoints as a special made-up class of XP events */
688 		struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);  in arm_cmn_read_dtm()  local
690 		u64 reg = readq_relaxed(xp->pmu_base + offset);  in arm_cmn_read_dtm()
848 		int wp_idx, xp = arm_cmn_node_to_xp(dn)->logid;  in arm_cmn_val_add_event()  local
850 		val->dtm_count[xp]++;  in arm_cmn_val_add_event()
851 		val->occupid[xp] = occupid;  in arm_cmn_val_add_event()
857 		val->wp[xp][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;  in arm_cmn_val_add_event()
896 		int wp_idx, wp_cmb, xp = arm_cmn_node_to_xp(dn)->logid;  in arm_cmn_validate_group()  local
898 		if (val.dtm_count[xp] == CMN_DTM_NUM_COUNTERS)  in arm_cmn_validate_group()
901 		if (occupid && val.occupid[xp] && occupid != val.occupid[xp])  in arm_cmn_validate_group()
908 		if (val.wp[xp][wp_idx])  in arm_cmn_validate_group()
911 		wp_cmb = val.wp[xp][wp_idx ^ 1];  in arm_cmn_validate_group()
943 	/* For watchpoints we need the actual XP node here */  in arm_cmn_event_init()
991 		struct arm_cmn_node *xp = arm_cmn_node_to_xp(hw->dn + i);  in arm_cmn_event_clear()  local
1000 		xp->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);  in arm_cmn_event_clear()
1001 		writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG);  in arm_cmn_event_clear()
1043 		struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);  in arm_cmn_event_add()  local
1048 		while (xp->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))  in arm_cmn_event_add()
1092 		xp->input_sel[dtm_idx] = input_sel;  in arm_cmn_event_add()
1094 		xp->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);  in arm_cmn_event_add()
1095 		xp->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;  in arm_cmn_event_add()
1096 		xp->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);  in arm_cmn_event_add()
1097 		reg = (u64)le32_to_cpu(xp->pmu_config_high) << 32 | xp->pmu_config_low;  in arm_cmn_event_add()
1098 		writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG);  in arm_cmn_event_add()
1234 static void arm_cmn_init_dtm(struct arm_cmn_node *xp)  in arm_cmn_init_dtm()  argument
1239 		xp->wp_event[i] = -1;  in arm_cmn_init_dtm()
1240 		writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i));  in arm_cmn_init_dtm()
1241 		writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i));  in arm_cmn_init_dtm()
1243 	xp->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;  in arm_cmn_init_dtm()
1244 	xp->dtc = -1;  in arm_cmn_init_dtm()
1250 	struct arm_cmn_node *xp;  in arm_cmn_init_dtc()  local
1261 	/* We do at least know that a DTC's XP must be in that DTC's domain */  in arm_cmn_init_dtc()
1262 	xp = arm_cmn_node_to_xp(dn);  in arm_cmn_init_dtc()
1263 	xp->dtc = idx;  in arm_cmn_init_dtc()
1378 		struct arm_cmn_node *xp = dn++;  in arm_cmn_discover()  local
1380 		arm_cmn_init_node_info(cmn, xp_offset[i], xp);  in arm_cmn_discover()
1381 		arm_cmn_init_dtm(xp);  in arm_cmn_discover()
1383 		 * Thanks to the order in which XP logical IDs seem to be  in arm_cmn_discover()
1385 		 * looking out for the XP at (0,1) without needing to know  in arm_cmn_discover()
1388 		if (xp->id == (1 << 3))  in arm_cmn_discover()
1389 			cmn->mesh_x = xp->logid;  in arm_cmn_discover()
1403 			 * but they don't go to regular XP DTMs, and they depend on  in arm_cmn_discover()
1446 	 * an XP at (0,1), thus we must have an Nx1 configuration.  in arm_cmn_discover()