Lines Matching +full:0 +full:x0000003c
26 WIDE_MODE = 0x0,
32 PASSTHROUGH = 0,
67 #define OCMEM_REG_HW_VERSION 0x00000000
68 #define OCMEM_REG_HW_PROFILE 0x00000004
70 #define OCMEM_REG_REGION_MODE_CTL 0x00001000
71 #define OCMEM_REGION_MODE_CTL_REG0_THIN 0x00000001
72 #define OCMEM_REGION_MODE_CTL_REG1_THIN 0x00000002
73 #define OCMEM_REGION_MODE_CTL_REG2_THIN 0x00000004
74 #define OCMEM_REGION_MODE_CTL_REG3_THIN 0x00000008
76 #define OCMEM_REG_GFX_MPU_START 0x00001004
77 #define OCMEM_REG_GFX_MPU_END 0x00001008
79 #define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_PREP(0x0000000f, (val))
80 #define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_PREP(0x00003f00, (val))
82 #define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE 0x00010000
83 #define OCMEM_HW_PROFILE_INTERLEAVING 0x00020000
84 #define OCMEM_REG_GEN_STATUS 0x0000000c
86 #define OCMEM_REG_PSGSC_STATUS 0x00000038
87 #define OCMEM_REG_PSGSC_CTL(i0) (0x0000003c + 0x1*(i0))
89 #define OCMEM_PSGSC_CTL_MACRO0_MODE(val) FIELD_PREP(0x00000007, (val))
90 #define OCMEM_PSGSC_CTL_MACRO1_MODE(val) FIELD_PREP(0x00000070, (val))
91 #define OCMEM_PSGSC_CTL_MACRO2_MODE(val) FIELD_PREP(0x00000700, (val))
92 #define OCMEM_PSGSC_CTL_MACRO3_MODE(val) FIELD_PREP(0x00007000, (val))
94 #define OCMEM_CLK_CORE_IDX 0
116 uint32_t region_mode_ctrl = 0x0; in update_ocmem()
120 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
132 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
136 data = OCMEM_PSGSC_CTL_MACRO0_MODE(region->macro_state[0]) | in update_ocmem()
149 return 0; in phys_to_offset()
167 unsigned long offset = 0; in update_range()
170 for (i = 0; i < ocmem->config->num_regions; i++) { in update_range()
176 for (j = 0; j < region->num_macros; j++) { in update_range()
194 devnode = of_parse_phandle(dev->of_node, "sram", 0); in of_get_ocmem()
237 buf->offset = 0; in ocmem_allocate()
257 dev_dbg(ocmem->dev, "using %ldK of OCMEM at 0x%08lx for client %d\n", in ocmem_allocate()
288 ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, 0x0); in ocmem_free()
289 ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END, 0x0); in ocmem_free()
339 WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0); in ocmem_dev_probe()
349 ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0); in ocmem_dev_probe()
375 for (i = 0; i < ocmem->config->num_regions; i++) { in ocmem_dev_probe()
395 for (j = 0; j < ARRAY_SIZE(region->macro_state); j++) in ocmem_dev_probe()
401 return 0; in ocmem_dev_probe()
412 return 0; in ocmem_dev_remove()