1 // SPDX-License-Identifier: GPL-2.0
17 #define NPCM_WTCLK	(BIT(10) | BIT(11))	/* Clock divider */
18 #define NPCM_WTE	BIT(7)			/* Enable */
19 #define NPCM_WTIE	BIT(6)			/* Enable irq */
20 #define NPCM_WTIS	(BIT(4) | BIT(5))	/* Interval selection */
21 #define NPCM_WTIF	BIT(3)			/* Interrupt flag*/
22 #define NPCM_WTRF	BIT(2)			/* Reset flag */
23 #define NPCM_WTRE	BIT(1)			/* Reset enable */
24 #define NPCM_WTR	BIT(0)			/* Reset counter */
34  * 10700   msec:    WTCLK=01 WTIS=11     VAL= 0x430
36  * 43000   msec:    WTCLK=11 WTIS=00     VAL= 0xC00
37  * 85600   msec:    WTCLK=10 WTIS=11     VAL= 0x830
38  * 172000  msec:    WTCLK=11 WTIS=01     VAL= 0xC10
39  * 687000  msec:    WTCLK=11 WTIS=10     VAL= 0xC20
40  * 2750000 msec:    WTCLK=11 WTIS=11     VAL= 0xC30
58 	val = readl(wdt->reg);  in npcm_wdt_ping()
59 	writel(val | NPCM_WTR, wdt->reg);  in npcm_wdt_ping()
69 	if (wdd->timeout < 2)  in npcm_wdt_start()
71 	else if (wdd->timeout < 3)  in npcm_wdt_start()
73 	else if (wdd->timeout < 6)  in npcm_wdt_start()
75 	else if (wdd->timeout < 11)  in npcm_wdt_start()
77 	else if (wdd->timeout < 22)  in npcm_wdt_start()
79 	else if (wdd->timeout < 44)  in npcm_wdt_start()
81 	else if (wdd->timeout < 87)  in npcm_wdt_start()
83 	else if (wdd->timeout < 173)  in npcm_wdt_start()
85 	else if (wdd->timeout < 688)  in npcm_wdt_start()
92 	writel(val, wdt->reg);  in npcm_wdt_start()
101 	writel(0, wdt->reg);  in npcm_wdt_stop()
110 		wdd->timeout = 1;  in npcm_wdt_set_timeout()
112 		wdd->timeout = 2;  in npcm_wdt_set_timeout()
114 		wdd->timeout = 5;  in npcm_wdt_set_timeout()
115 	else if (timeout < 11)  in npcm_wdt_set_timeout()
116 		wdd->timeout = 10;  in npcm_wdt_set_timeout()
118 		wdd->timeout = 21;  in npcm_wdt_set_timeout()
120 		wdd->timeout = 43;  in npcm_wdt_set_timeout()
122 		wdd->timeout = 86;  in npcm_wdt_set_timeout()
124 		wdd->timeout = 172;  in npcm_wdt_set_timeout()
126 		wdd->timeout = 687;  in npcm_wdt_set_timeout()
128 		wdd->timeout = 2750;  in npcm_wdt_set_timeout()
140 	watchdog_notify_pretimeout(&wdt->wdd);  in npcm_wdt_interrupt()
150 	writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);  in npcm_wdt_restart()
160 	return readl(wdt->reg) & NPCM_WTE;  in npcm_is_running()
181 	struct device *dev = &pdev->dev;  in npcm_wdt_probe()
188 		return -ENOMEM;  in npcm_wdt_probe()
190 	wdt->reg = devm_platform_ioremap_resource(pdev, 0);  in npcm_wdt_probe()
191 	if (IS_ERR(wdt->reg))  in npcm_wdt_probe()
192 		return PTR_ERR(wdt->reg);  in npcm_wdt_probe()
198 	wdt->wdd.info = &npcm_wdt_info;  in npcm_wdt_probe()
199 	wdt->wdd.ops = &npcm_wdt_ops;  in npcm_wdt_probe()
200 	wdt->wdd.min_timeout = 1;  in npcm_wdt_probe()
201 	wdt->wdd.max_timeout = 2750;  in npcm_wdt_probe()
202 	wdt->wdd.parent = dev;  in npcm_wdt_probe()
204 	wdt->wdd.timeout = 86;  in npcm_wdt_probe()
205 	watchdog_init_timeout(&wdt->wdd, 0, dev);  in npcm_wdt_probe()
208 	npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);  in npcm_wdt_probe()
210 	if (npcm_is_running(&wdt->wdd)) {  in npcm_wdt_probe()
211 		/* Restart with the default or device-tree specified timeout */  in npcm_wdt_probe()
212 		npcm_wdt_start(&wdt->wdd);  in npcm_wdt_probe()
213 		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);  in npcm_wdt_probe()
221 	ret = devm_watchdog_register_device(dev, &wdt->wdd);  in npcm_wdt_probe()
232 	{.compatible = "nuvoton,npcm750-wdt"},
241 		.name	= "npcm-wdt",