Lines Matching +full:4 +full:- +full:16

1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
14 #define DEV_CLOCK_CFG_PCS_RX_RST                          BIT(4)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA                       BIT(4)
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x)        (((x) << 4) & GENMASK(11, 4))
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M         GENMASK(11, 4)
40 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x)      (((x) & GENMASK(11, 4)) >> 4)
44 #define DEV_MAC_ENA_CFG_RX_ENA                            BIT(4)
48 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA                    BIT(4)
51 #define DEV_MAC_TAGS_CFG_TAG_ID(x)                        (((x) << 16) & GENMASK(31, 16))
52 #define DEV_MAC_TAGS_CFG_TAG_ID_M                         GENMASK(31, 16)
53 #define DEV_MAC_TAGS_CFG_TAG_ID_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
61 #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG                    BIT(16)
65 #define DEV_MAC_IFG_CFG_RX_IFG2(x)                        (((x) << 4) & GENMASK(7, 4))
66 #define DEV_MAC_IFG_CFG_RX_IFG2_M                         GENMASK(7, 4)
67 #define DEV_MAC_IFG_CFG_RX_IFG2_X(x)                      (((x) & GENMASK(7, 4)) >> 4)
74 #define DEV_MAC_HDX_CFG_SEED(x)                           (((x) << 16) & GENMASK(23, 16))
75 #define DEV_MAC_HDX_CFG_SEED_M                            GENMASK(23, 16)
76 #define DEV_MAC_HDX_CFG_SEED_X(x)                         (((x) & GENMASK(23, 16)) >> 16)
82 #define DEV_MAC_DBG_CFG_TBI_MODE                          BIT(4)
90 #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY               BIT(4)
96 #define PCS1G_CFG_LINK_STATUS_TYPE                        BIT(4)
100 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA                    BIT(4)
104 #define PCS1G_SD_CFG_SD_POL                               BIT(4)
107 #define PCS1G_ANEG_CFG_ADV_ABILITY(x)                     (((x) << 16) & GENMASK(31, 16))
108 #define PCS1G_ANEG_CFG_ADV_ABILITY_M                      GENMASK(31, 16)
109 #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x)                   (((x) & GENMASK(31, 16)) >> 16)
114 #define PCS1G_ANEG_NP_CFG_NP_TX(x)                        (((x) << 16) & GENMASK(31, 16))
115 #define PCS1G_ANEG_NP_CFG_NP_TX_M                         GENMASK(31, 16)
116 #define PCS1G_ANEG_NP_CFG_NP_TX_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
119 #define PCS1G_LB_CFG_RA_ENA                               BIT(4)
127 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x)               (((x) << 16) & GENMASK(31, 16))
128 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M                GENMASK(31, 16)
129 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x)             (((x) & GENMASK(31, 16)) >> 16)
130 #define PCS1G_ANEG_STATUS_PR                              BIT(4)
138 #define PCS1G_LINK_STATUS_LINK_STATUS                     BIT(4)
141 #define PCS1G_STICKY_LINK_DOWN_STICKY                     BIT(4)
146 #define PCS1G_LPI_CFG_LPI_TESTMODE                        BIT(16)
147 #define PCS1G_LPI_CFG_LPI_RX_WTIM(x)                      (((x) << 4) & GENMASK(5, 4))
148 #define PCS1G_LPI_CFG_LPI_RX_WTIM_M                       GENMASK(5, 4)
149 #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x)                    (((x) & GENMASK(5, 4)) >> 4)
152 #define PCS1G_LPI_STATUS_RX_LPI_FAIL                      BIT(16)
156 #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY              BIT(4)
163 #define PCS1G_TSTPAT_STATUS_JTP_ERR                       BIT(4)
170 #define DEV_PCS_FX100_CFG_SWAP_MII_ENA                    BIT(16)
178 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x)                (((x) << 4) & GENMASK(7, 4))
179 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M                 GENMASK(7, 4)
180 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x)              (((x) & GENMASK(7, 4)) >> 4)
192 #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY             BIT(4)