3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22    MA  02111-1307, USA.
26  Translation from C++ and adaptation for use in ALSA-Driver
33 static int set_input_clock(struct echoaudio *chip, u16 clock);
35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
45 		return -ENODEV;  in init_hw()
48 		dev_err(chip->card->dev,  in init_hw()
49 			"init_hw - could not initialize DSP comm page\n");  in init_hw()
53 	chip->device_id = device_id;  in init_hw()
54 	chip->subdevice_id = subdevice_id;  in init_hw()
55 	chip->bad_board = true;  in init_hw()
56 	chip->input_clock_types =  in init_hw()
59 	chip->digital_modes =  in init_hw()
65 	if (chip->device_id == DEVICE_ID_56361)  in init_hw()
66 		chip->dsp_code_to_load = FW_MONA_361_DSP;  in init_hw()
68 		chip->dsp_code_to_load = FW_MONA_301_DSP;  in init_hw()
72 	chip->bad_board = false;  in init_hw()
81 	chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;  in set_mixer_defaults()
82 	chip->professional_spdif = false;  in set_mixer_defaults()
83 	chip->digital_in_automute = true;  in set_mixer_defaults()
93 	/* Map the DSP clock detect bits to the generic driver clock  in detect_input_clocks()
95 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);  in detect_input_clocks()
121 	if (chip->asic_loaded)  in load_asic()
126 	if (chip->device_id == DEVICE_ID_56361)  in load_asic()
135 	chip->asic_code = asic;  in load_asic()
147 	/* Set up the control register if the load succeeded -  in load_asic()
148 	   48 kHz, internal clock, S/PDIF RCA mode */  in load_asic()
159 /* Depending on what digital mode you want, Mona needs different ASICs
160 loaded.  This function checks the ASIC needed for the new mode and sees
167 	/* Check the clock detect bits to see if this is  in switch_asic()
168 	a single-speed clock or a double-speed clock; load  in switch_asic()
170 	if (chip->device_id == DEVICE_ID_56361) {  in switch_asic()
182 	if (asic != chip->asic_code) {  in switch_asic()
188 		chip->asic_code = asic;  in switch_asic()
198 	u32 control_reg, clock;  in set_sample_rate()  local
202 	/* Only set the clock for internal mode. */  in set_sample_rate()
203 	if (chip->input_clock != ECHO_CLOCK_INTERNAL) {  in set_sample_rate()
204 		dev_dbg(chip->card->dev,  in set_sample_rate()
205 			"Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");  in set_sample_rate()
207 		chip->comm_page->sample_rate = cpu_to_le32(rate);  in set_sample_rate()
208 		chip->sample_rate = rate;  in set_sample_rate()
214 		if (chip->digital_mode == DIGITAL_MODE_ADAT)  in set_sample_rate()
215 			return -EINVAL;  in set_sample_rate()
216 		if (chip->device_id == DEVICE_ID_56361)  in set_sample_rate()
221 		if (chip->device_id == DEVICE_ID_56361)  in set_sample_rate()
228 	if (asic != chip->asic_code) {  in set_sample_rate()
231 		spin_unlock_irq(&chip->lock);  in set_sample_rate()
234 		spin_lock_irq(&chip->lock);  in set_sample_rate()
238 		chip->asic_code = asic;  in set_sample_rate()
243 	clock = 0;  in set_sample_rate()
244 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
250 		clock = GML_96KHZ;  in set_sample_rate()
253 		clock = GML_88KHZ;  in set_sample_rate()
256 		clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;  in set_sample_rate()
259 		clock = GML_44KHZ;  in set_sample_rate()
260 		/* Professional mode */  in set_sample_rate()
262 			clock |= GML_SPDIF_SAMPLE_RATE0;  in set_sample_rate()
265 		clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |  in set_sample_rate()
269 		clock = GML_22KHZ;  in set_sample_rate()
272 		clock = GML_16KHZ;  in set_sample_rate()
275 		clock = GML_11KHZ;  in set_sample_rate()
278 		clock = GML_8KHZ;  in set_sample_rate()
281 		dev_err(chip->card->dev,  in set_sample_rate()
283 		return -EINVAL;  in set_sample_rate()
286 	control_reg |= clock;  in set_sample_rate()
288 	chip->comm_page->sample_rate = cpu_to_le32(rate);	/* ignored by the DSP */  in set_sample_rate()
289 	chip->sample_rate = rate;  in set_sample_rate()
290 	dev_dbg(chip->card->dev,  in set_sample_rate()
291 		"set_sample_rate: %d clock %d\n", rate, clock);  in set_sample_rate()
298 static int set_input_clock(struct echoaudio *chip, u16 clock)  in set_input_clock()  argument
303 	/* Mask off the clock select bits */  in set_input_clock()
304 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
306 	clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);  in set_input_clock()
308 	switch (clock) {  in set_input_clock()
310 		chip->input_clock = ECHO_CLOCK_INTERNAL;  in set_input_clock()
311 		return set_sample_rate(chip, chip->sample_rate);  in set_input_clock()
313 		if (chip->digital_mode == DIGITAL_MODE_ADAT)  in set_input_clock()
314 			return -EAGAIN;  in set_input_clock()
315 		spin_unlock_irq(&chip->lock);  in set_input_clock()
318 		spin_lock_irq(&chip->lock);  in set_input_clock()
328 		spin_unlock_irq(&chip->lock);  in set_input_clock()
331 		spin_lock_irq(&chip->lock);  in set_input_clock()
341 		dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n");  in set_input_clock()
342 		if (chip->digital_mode != DIGITAL_MODE_ADAT)  in set_input_clock()
343 			return -EAGAIN;  in set_input_clock()
348 		dev_err(chip->card->dev,  in set_input_clock()
349 			"Input clock 0x%x not supported for Mona\n", clock);  in set_input_clock()
350 		return -EINVAL;  in set_input_clock()
353 	chip->input_clock = clock;  in set_input_clock()
359 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)  in dsp_set_digital_mode()  argument
364 	/* Set clock to "internal" if it's not compatible with the new mode */  in dsp_set_digital_mode()
366 	switch (mode) {  in dsp_set_digital_mode()
369 		if (chip->input_clock == ECHO_CLOCK_ADAT)  in dsp_set_digital_mode()
373 		if (chip->input_clock == ECHO_CLOCK_SPDIF)  in dsp_set_digital_mode()
377 		dev_err(chip->card->dev,  in dsp_set_digital_mode()
378 			"Digital mode not supported: %d\n", mode);  in dsp_set_digital_mode()
379 		return -EINVAL;  in dsp_set_digital_mode()
382 	spin_lock_irq(&chip->lock);  in dsp_set_digital_mode()
385 		chip->sample_rate = 48000;  in dsp_set_digital_mode()
389 	/* Clear the current digital mode */  in dsp_set_digital_mode()
390 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
394 	switch (mode) {  in dsp_set_digital_mode()
404 		if (chip->asic_code == FW_MONA_361_1_ASIC96 ||  in dsp_set_digital_mode()
405 		    chip->asic_code == FW_MONA_301_1_ASIC96) {  in dsp_set_digital_mode()
414 	spin_unlock_irq(&chip->lock);  in dsp_set_digital_mode()
417 	chip->digital_mode = mode;  in dsp_set_digital_mode()
419 	dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);  in dsp_set_digital_mode()