Lines Matching +full:switch +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
253 switch (reg) { in max98090_volatile_register()
266 switch (reg) { in max98090_readable_register()
280 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
284 dev_err(max98090->component->dev, in max98090_reset()
301 -600, 600, 0);
304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
320 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
321 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
325 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
326 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
327 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
328 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
333 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
334 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
335 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
336 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
341 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
342 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
343 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
354 (struct soc_mixer_control *)kcontrol->private_value; in max98090_get_enab_tlv()
355 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_get_enab_tlv()
356 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_get_enab_tlv()
359 switch (mc->reg) { in max98090_get_enab_tlv()
361 select = &(max98090->pa1en); in max98090_get_enab_tlv()
364 select = &(max98090->pa2en); in max98090_get_enab_tlv()
367 select = &(max98090->sidetone); in max98090_get_enab_tlv()
370 return -EINVAL; in max98090_get_enab_tlv()
373 val = (val >> mc->shift) & mask; in max98090_get_enab_tlv()
377 val = val - 1; in max98090_get_enab_tlv()
384 ucontrol->value.integer.value[0] = val; in max98090_get_enab_tlv()
394 (struct soc_mixer_control *)kcontrol->private_value; in max98090_put_enab_tlv()
395 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_put_enab_tlv()
396 unsigned int sel = ucontrol->value.integer.value[0]; in max98090_put_enab_tlv()
397 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_put_enab_tlv()
400 switch (mc->reg) { in max98090_put_enab_tlv()
402 select = &(max98090->pa1en); in max98090_put_enab_tlv()
405 select = &(max98090->pa2en); in max98090_put_enab_tlv()
408 select = &(max98090->sidetone); in max98090_put_enab_tlv()
411 return -EINVAL; in max98090_put_enab_tlv()
414 val = (val >> mc->shift) & mask; in max98090_put_enab_tlv()
426 snd_soc_component_update_bits(component, mc->reg, in max98090_put_enab_tlv()
427 mask << mc->shift, in max98090_put_enab_tlv()
428 sel << mc->shift); in max98090_put_enab_tlv()
512 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
516 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
521 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
525 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
529 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
534 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
538 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
541 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
545 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
549 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
551 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
554 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
557 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
561 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
564 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
569 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
573 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
575 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
577 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
578 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
579 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
582 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
584 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
586 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
589 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
592 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
595 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
598 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
599 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
600 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
601 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
602 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
603 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
605 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
608 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
612 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
616 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
622 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
625 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
633 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
636 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
640 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
643 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
647 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
650 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
654 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
658 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
663 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
665 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
667 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
670 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
672 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
675 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
677 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
680 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
681 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
683 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
685 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
688 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
689 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
696 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
701 M98090_FLT_DMIC34HPF_NUM - 1, 0),
704 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
707 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
711 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
714 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
719 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
720 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
724 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
730 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_micinput_event()
733 unsigned int val = snd_soc_component_read(component, w->reg); in max98090_micinput_event()
735 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { in max98090_micinput_event()
742 max98090->pa1en = val - 1; /* Update for volatile */ in max98090_micinput_event()
744 max98090->pa2en = val - 1; /* Update for volatile */ in max98090_micinput_event()
748 switch (event) { in max98090_micinput_event()
751 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
752 val = max98090->pa1en + 1; in max98090_micinput_event()
754 val = max98090->pa2en + 1; in max98090_micinput_event()
761 return -EINVAL; in max98090_micinput_event()
764 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
765 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, in max98090_micinput_event()
768 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, in max98090_micinput_event()
777 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_shdn_event()
781 max98090->shdn_pending = true; in max98090_shdn_event()
814 /* LINEA mixer switch */
816 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
818 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
820 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
822 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
826 /* LINEB mixer switch */
828 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
830 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
832 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
834 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
838 /* Left ADC mixer switch */
840 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
842 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
844 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
846 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
848 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
850 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
852 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
856 /* Right ADC mixer switch */
858 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
860 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
862 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
864 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
866 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
868 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
870 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
930 /* Left speaker mixer switch */
933 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
935 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
937 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
939 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
941 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
943 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
947 /* Right speaker mixer switch */
950 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
952 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
954 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
956 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
958 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
960 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
964 /* Left headphone mixer switch */
966 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
968 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
970 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
972 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
974 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
976 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
980 /* Right headphone mixer switch */
982 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
984 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
986 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
988 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
990 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
992 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
996 /* Left receiver mixer switch */
998 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1000 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1002 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1004 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1006 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1008 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1012 /* Right receiver mixer switch */
1014 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1016 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1018 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1020 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1022 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1024 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1259 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1260 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1261 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1262 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1263 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1264 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1265 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1268 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1269 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1270 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1271 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1272 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1273 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1274 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1277 {"LINEA Mixer", "IN1 Switch", "IN1"},
1278 {"LINEA Mixer", "IN3 Switch", "IN3"},
1279 {"LINEA Mixer", "IN5 Switch", "IN5"},
1280 {"LINEA Mixer", "IN34 Switch", "IN34"},
1283 {"LINEB Mixer", "IN2 Switch", "IN2"},
1284 {"LINEB Mixer", "IN4 Switch", "IN4"},
1285 {"LINEB Mixer", "IN6 Switch", "IN6"},
1286 {"LINEB Mixer", "IN56 Switch", "IN56"},
1337 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1338 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1339 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1340 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1341 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1342 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1345 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1346 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1347 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1348 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1349 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1350 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1353 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1354 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1355 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1356 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1357 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1358 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1361 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1362 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1363 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1364 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1365 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1366 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1369 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1370 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1371 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1372 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1373 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1374 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1377 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1378 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1379 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1380 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1381 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1382 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1434 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1445 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1488 if (!max98090->sysclk) { in max98090_configure_bclk()
1489 dev_err(component->dev, "No SYSCLK configured\n"); in max98090_configure_bclk()
1493 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1494 dev_err(component->dev, "No audio clocks configured\n"); in max98090_configure_bclk()
1506 if ((pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1507 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1508 dev_dbg(component->dev, in max98090_configure_bclk()
1523 if ((user_pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1524 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1525 dev_dbg(component->dev, in max98090_configure_bclk()
1527 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", in max98090_configure_bclk()
1562 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1563 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1564 do_div(ni, (unsigned long long int)max98090->sysclk); in max98090_configure_bclk()
1565 dev_info(component->dev, "No better method found\n"); in max98090_configure_bclk()
1566 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); in max98090_configure_bclk()
1575 struct snd_soc_component *component = codec_dai->component; in max98090_dai_set_fmt()
1580 max98090->dai_fmt = fmt; in max98090_dai_set_fmt()
1581 cdata = &max98090->dai[0]; in max98090_dai_set_fmt()
1583 if (fmt != cdata->fmt) { in max98090_dai_set_fmt()
1584 cdata->fmt = fmt; in max98090_dai_set_fmt()
1587 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { in max98090_dai_set_fmt()
1589 /* Set to slave mode PLL - MAS mode off */ in max98090_dai_set_fmt()
1596 max98090->master = false; in max98090_dai_set_fmt()
1600 if (max98090->tdm_slots == 4) { in max98090_dai_set_fmt()
1604 } else if (max98090->tdm_slots == 3) { in max98090_dai_set_fmt()
1613 max98090->master = true; in max98090_dai_set_fmt()
1618 dev_err(component->dev, "DAI clock mode unsupported"); in max98090_dai_set_fmt()
1619 return -EINVAL; in max98090_dai_set_fmt()
1624 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { in max98090_dai_set_fmt()
1636 dev_err(component->dev, "DAI format unsupported"); in max98090_dai_set_fmt()
1637 return -EINVAL; in max98090_dai_set_fmt()
1640 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { in max98090_dai_set_fmt()
1653 dev_err(component->dev, "DAI invert mode unsupported"); in max98090_dai_set_fmt()
1654 return -EINVAL; in max98090_dai_set_fmt()
1663 if (max98090->tdm_slots > 1) in max98090_dai_set_fmt()
1676 struct snd_soc_component *component = codec_dai->component; in max98090_set_tdm_slot()
1679 cdata = &max98090->dai[0]; in max98090_set_tdm_slot()
1682 return -EINVAL; in max98090_set_tdm_slot()
1684 max98090->tdm_slots = slots; in max98090_set_tdm_slot()
1685 max98090->tdm_width = slot_width; in max98090_set_tdm_slot()
1687 if (max98090->tdm_slots > 1) { in max98090_set_tdm_slot()
1703 cdata->fmt = 0; in max98090_set_tdm_slot()
1704 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); in max98090_set_tdm_slot()
1715 switch (level) { in max98090_set_bias_level()
1727 if (IS_ERR(max98090->mclk)) in max98090_set_bias_level()
1731 clk_disable_unprepare(max98090->mclk); in max98090_set_bias_level()
1733 ret = clk_prepare_enable(max98090->mclk); in max98090_set_bias_level()
1741 ret = regcache_sync(max98090->regmap); in max98090_set_bias_level()
1743 dev_err(component->dev, in max98090_set_bias_level()
1751 /* Set internal pull-up to lowest power mode */ in max98090_set_bias_level()
1754 regcache_mark_dirty(max98090->regmap); in max98090_set_bias_level()
1769 int freq; member
1774 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1778 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1779 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1780 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1781 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1782 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1783 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1789 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1790 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1791 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1792 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1793 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1794 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1800 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1801 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1802 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1803 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1804 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1805 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1811 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1812 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1813 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1814 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1815 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1816 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1822 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1823 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1824 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1825 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1826 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1827 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1840 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); in max98090_find_divisor()
1862 m1 = pclk - dmic_table[i-1].pclk; in max98090_find_closest_pclk()
1863 m2 = dmic_table[i].pclk - pclk; in max98090_find_closest_pclk()
1865 return i - 1; in max98090_find_closest_pclk()
1871 return -EINVAL; in max98090_find_closest_pclk()
1889 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { in max98090_configure_dmic()
1894 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; in max98090_configure_dmic()
1897 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, in max98090_configure_dmic()
1901 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, in max98090_configure_dmic()
1912 struct snd_soc_component *component = dai->component; in max98090_dai_startup()
1914 unsigned int fmt = max98090->dai_fmt; in max98090_dai_startup()
1916 /* Remove 24-bit format support if it is not in right justified mode. */ in max98090_dai_startup()
1918 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; in max98090_dai_startup()
1919 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); in max98090_dai_startup()
1928 struct snd_soc_component *component = dai->component; in max98090_dai_hw_params()
1932 cdata = &max98090->dai[0]; in max98090_dai_hw_params()
1933 max98090->bclk = snd_soc_params_to_bclk(params); in max98090_dai_hw_params()
1935 max98090->bclk *= 2; in max98090_dai_hw_params()
1937 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1939 switch (params_width(params)) { in max98090_dai_hw_params()
1945 return -EINVAL; in max98090_dai_hw_params()
1948 if (max98090->master) in max98090_dai_hw_params()
1951 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
1954 if (max98090->lrclk < 24000) in max98090_dai_hw_params()
1962 if (max98090->lrclk < 50000) in max98090_dai_hw_params()
1969 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, in max98090_dai_hw_params()
1970 max98090->lrclk); in max98090_dai_hw_params()
1979 int clk_id, unsigned int freq, int dir) in max98090_dai_set_sysclk() argument
1981 struct snd_soc_component *component = dai->component; in max98090_dai_set_sysclk()
1985 if (freq == max98090->sysclk) in max98090_dai_set_sysclk()
1988 if (!IS_ERR(max98090->mclk)) { in max98090_dai_set_sysclk()
1989 freq = clk_round_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
1990 clk_set_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
1998 if ((freq >= 10000000) && (freq <= 20000000)) { in max98090_dai_set_sysclk()
2001 max98090->pclk = freq; in max98090_dai_set_sysclk()
2002 } else if ((freq > 20000000) && (freq <= 40000000)) { in max98090_dai_set_sysclk()
2005 max98090->pclk = freq >> 1; in max98090_dai_set_sysclk()
2006 } else if ((freq > 40000000) && (freq <= 60000000)) { in max98090_dai_set_sysclk()
2009 max98090->pclk = freq >> 2; in max98090_dai_set_sysclk()
2011 dev_err(component->dev, "Invalid master clock frequency\n"); in max98090_dai_set_sysclk()
2012 return -EINVAL; in max98090_dai_set_sysclk()
2015 max98090->sysclk = freq; in max98090_dai_set_sysclk()
2023 struct snd_soc_component *component = codec_dai->component; in max98090_dai_mute()
2036 struct snd_soc_component *component = dai->component; in max98090_dai_trigger()
2039 switch (cmd) { in max98090_dai_trigger()
2043 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2045 &max98090->pll_det_enable_work, in max98090_dai_trigger()
2051 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2052 schedule_work(&max98090->pll_det_disable_work); in max98090_dai_trigger()
2066 struct snd_soc_component *component = max98090->component; in max98090_pll_det_enable_work()
2075 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_pll_det_enable_work()
2081 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_pll_det_enable_work()
2085 &max98090->jack_work, in max98090_pll_det_enable_work()
2098 struct snd_soc_component *component = max98090->component; in max98090_pll_det_disable_work()
2100 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_pll_det_disable_work()
2109 struct snd_soc_component *component = max98090->component; in max98090_pll_work()
2116 dev_info_ratelimited(component->dev, "PLL unlocked\n"); in max98090_pll_work()
2148 struct snd_soc_component *component = max98090->component; in max98090_jack_work()
2153 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { in max98090_jack_work()
2172 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { in max98090_jack_work()
2174 dev_dbg(component->dev, "No Headset Detected\n"); in max98090_jack_work()
2176 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_jack_work()
2183 if (max98090->jack_state == in max98090_jack_work()
2186 dev_dbg(component->dev, in max98090_jack_work()
2203 dev_dbg(component->dev, "Headphone Detected\n"); in max98090_jack_work()
2205 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; in max98090_jack_work()
2212 dev_dbg(component->dev, "Headset Detected\n"); in max98090_jack_work()
2214 max98090->jack_state = M98090_JACK_STATE_HEADSET; in max98090_jack_work()
2221 dev_dbg(component->dev, "Unrecognized Jack Status\n"); in max98090_jack_work()
2225 snd_soc_jack_report(max98090->jack, status, in max98090_jack_work()
2232 struct snd_soc_component *component = max98090->component; in max98090_interrupt()
2241 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); in max98090_interrupt()
2243 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_interrupt()
2246 dev_err(component->dev, in max98090_interrupt()
2252 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); in max98090_interrupt()
2255 dev_err(component->dev, in max98090_interrupt()
2261 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", in max98090_interrupt()
2270 dev_err(component->dev, "M98090_CLD_MASK\n"); in max98090_interrupt()
2273 dev_dbg(component->dev, "M98090_SLD_MASK\n"); in max98090_interrupt()
2276 dev_dbg(component->dev, "M98090_ULK_MASK\n"); in max98090_interrupt()
2281 dev_dbg(component->dev, "M98090_JDET_MASK\n"); in max98090_interrupt()
2283 pm_wakeup_event(component->dev, 100); in max98090_interrupt()
2286 &max98090->jack_work, in max98090_interrupt()
2291 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); in max98090_interrupt()
2294 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); in max98090_interrupt()
2300 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2317 dev_dbg(component->dev, "max98090_mic_detect\n"); in max98090_mic_detect()
2319 max98090->jack = jack; in max98090_mic_detect()
2331 snd_soc_jack_report(max98090->jack, 0, in max98090_mic_detect()
2335 &max98090->jack_work, in max98090_mic_detect()
2386 dev_dbg(component->dev, "max98090_probe\n"); in max98090_probe()
2388 max98090->mclk = devm_clk_get(component->dev, "mclk"); in max98090_probe()
2389 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) in max98090_probe()
2390 return -EPROBE_DEFER; in max98090_probe()
2392 max98090->component = component; in max98090_probe()
2399 max98090->sysclk = (unsigned)-1; in max98090_probe()
2400 max98090->pclk = (unsigned)-1; in max98090_probe()
2401 max98090->master = false; in max98090_probe()
2403 cdata = &max98090->dai[0]; in max98090_probe()
2404 cdata->rate = (unsigned)-1; in max98090_probe()
2405 cdata->fmt = (unsigned)-1; in max98090_probe()
2407 max98090->lin_state = 0; in max98090_probe()
2408 max98090->pa1en = 0; in max98090_probe()
2409 max98090->pa2en = 0; in max98090_probe()
2413 dev_err(component->dev, "Failed to read device revision: %d\n", in max98090_probe()
2420 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); in max98090_probe()
2423 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); in max98090_probe()
2426 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); in max98090_probe()
2429 if (max98090->devtype != devtype) { in max98090_probe()
2430 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); in max98090_probe()
2431 max98090->devtype = devtype; in max98090_probe()
2434 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_probe()
2436 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); in max98090_probe()
2437 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, in max98090_probe()
2439 INIT_WORK(&max98090->pll_det_disable_work, in max98090_probe()
2468 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); in max98090_probe()
2471 dev_info(component->dev, "use default 2.8v micbias\n"); in max98090_probe()
2473 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); in max98090_probe()
2490 cancel_delayed_work_sync(&max98090->jack_work); in max98090_remove()
2491 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_remove()
2492 cancel_work_sync(&max98090->pll_det_disable_work); in max98090_remove()
2493 max98090->component = NULL; in max98090_remove()
2501 if (max98090->shdn_pending) { in max98090_seq_notifier()
2507 max98090->shdn_pending = false; in max98090_seq_notifier()
2544 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), in max98090_i2c_probe()
2547 return -ENOMEM; in max98090_i2c_probe()
2549 if (ACPI_HANDLE(&i2c->dev)) { in max98090_i2c_probe()
2550 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, in max98090_i2c_probe()
2551 &i2c->dev); in max98090_i2c_probe()
2553 dev_err(&i2c->dev, "No driver data\n"); in max98090_i2c_probe()
2554 return -EINVAL; in max98090_i2c_probe()
2556 driver_data = acpi_id->driver_data; in max98090_i2c_probe()
2558 driver_data = i2c_id->driver_data; in max98090_i2c_probe()
2561 max98090->devtype = driver_data; in max98090_i2c_probe()
2563 max98090->pdata = i2c->dev.platform_data; in max98090_i2c_probe()
2565 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", in max98090_i2c_probe()
2566 &max98090->dmic_freq); in max98090_i2c_probe()
2568 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; in max98090_i2c_probe()
2570 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); in max98090_i2c_probe()
2571 if (IS_ERR(max98090->regmap)) { in max98090_i2c_probe()
2572 ret = PTR_ERR(max98090->regmap); in max98090_i2c_probe()
2573 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in max98090_i2c_probe()
2577 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in max98090_i2c_probe()
2581 dev_err(&i2c->dev, "request_irq failed: %d\n", in max98090_i2c_probe()
2586 ret = devm_snd_soc_register_component(&i2c->dev, in max98090_i2c_probe()
2595 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); in max98090_i2c_shutdown()
2601 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2603 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2620 regcache_cache_only(max98090->regmap, false); in max98090_runtime_resume()
2624 regcache_sync(max98090->regmap); in max98090_runtime_resume()
2633 regcache_cache_only(max98090->regmap, true); in max98090_runtime_suspend()
2645 regcache_mark_dirty(max98090->regmap); in max98090_resume()
2650 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_resume()
2652 regcache_sync(max98090->regmap); in max98090_resume()