Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
14 #include <dt-bindings/sound/rt5640.h>
21 /* I/O - Output */
26 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
37 /* Mixer - D-D */
47 /* Mixer - ADC */
52 /* Mixer - DAC */
77 /* Format - ADC/DAC */
83 /* Function - Analog */
101 /* Function - Digital */
190 #define RT5640_L_VOL_MASK (0x3f << 8)
191 #define RT5640_L_VOL_SFT 8
204 #define RT5640_BST_SFT1 12
205 #define RT5640_BST_SFT2 8
216 #define RT5640_INL_VOL_MASK (0x1f << 8)
217 #define RT5640_INL_VOL_SFT 8
226 #define RT5640_DAC_L1_VOL_MASK (0xff << 8)
227 #define RT5640_DAC_L1_VOL_SFT 8
232 #define RT5640_DAC_L2_VOL_MASK (0xff << 8)
233 #define RT5640_DAC_L2_VOL_SFT 8
240 #define RT5640_M_DAC_R2_VOL (0x1 << 12)
241 #define RT5640_M_DAC_R2_VOL_SFT 12
244 #define RT5640_ADC_L_VOL_MASK (0x7f << 8)
245 #define RT5640_ADC_L_VOL_SFT 8
250 #define RT5640_MONO_ADC_L_VOL_MASK (0x7f << 8)
251 #define RT5640_MONO_ADC_L_VOL_SFT 8
258 #define RT5640_ADC_R_BST_MASK (0x3 << 12)
259 #define RT5640_ADC_R_BST_SFT 12
268 #define RT5640_ADC_1_SRC_MASK (0x1 << 12)
269 #define RT5640_ADC_1_SRC_SFT 12
270 #define RT5640_ADC_1_SRC_ADC (0x1 << 12)
271 #define RT5640_ADC_1_SRC_DACMIX (0x0 << 12)
287 #define RT5640_MONO_ADC_L1_SRC_MASK (0x1 << 12)
288 #define RT5640_MONO_ADC_L1_SRC_SFT 12
289 #define RT5640_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
290 #define RT5640_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
325 #define RT5640_M_DAC_L2 (0x1 << 12)
326 #define RT5640_M_DAC_L2_SFT 12
347 #define RT5640_M_DAC_L2_MONO_L (0x1 << 12)
348 #define RT5640_M_DAC_L2_MONO_L_SFT 12
375 #define RT5640_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
376 #define RT5640_DAC_L2_DAC_L_VOL_SFT 12
383 #define RT5640_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
384 #define RT5640_DAC_R2_DAC_R_VOL_SFT 8
403 #define RT5640_DAC_R2_SEL_MASK (0x3 << 12)
404 #define RT5640_DAC_R2_SEL_SFT 12
405 #define RT5640_DAC_R2_SEL_IF2 (0x0 << 12)
406 #define RT5640_DAC_R2_SEL_IF3 (0x1 << 12)
407 #define RT5640_DAC_R2_SEL_TXDC (0x2 << 12)
416 #define RT5640_RXDC_SEL_MASK (0x3 << 8)
417 #define RT5640_RXDC_SEL_SFT 8
418 #define RT5640_RXDC_SEL_NOR (0x0 << 8)
419 #define RT5640_RXDC_SEL_L2R (0x1 << 8)
420 #define RT5640_RXDC_SEL_R2L (0x2 << 8)
421 #define RT5640_RXDC_SEL_SWAP (0x3 << 8)
448 #define RT5640_IF1_ADC_SEL_MASK (0x3 << 12)
449 #define RT5640_IF1_ADC_SEL_SFT 12
450 #define RT5640_IF1_ADC_SEL_NOR (0x0 << 12)
451 #define RT5640_IF1_ADC_SEL_SWAP (0x1 << 12)
452 #define RT5640_IF1_ADC_SEL_L2R (0x2 << 12)
453 #define RT5640_IF1_ADC_SEL_R2L (0x3 << 12)
460 #define RT5640_IF2_ADC_SEL_MASK (0x3 << 8)
461 #define RT5640_IF2_ADC_SEL_SFT 8
462 #define RT5640_IF2_ADC_SEL_NOR (0x0 << 8)
463 #define RT5640_IF2_ADC_SEL_SWAP (0x1 << 8)
464 #define RT5640_IF2_ADC_SEL_L2R (0x2 << 8)
465 #define RT5640_IF2_ADC_SEL_R2L (0x3 << 8)
550 #define RT5640_G_HPOMIX_MASK (0x1 << 12)
551 #define RT5640_G_HPOMIX_SFT 12
556 #define RT5640_G_IN_L_SM_L_MASK (0x3 << 12)
557 #define RT5640_G_IN_L_SM_L_SFT 12
560 #define RT5640_G_DAC_L2_SM_L_MASK (0x3 << 8)
561 #define RT5640_G_DAC_L2_SM_L_SFT 8
578 #define RT5640_G_IN_R_SM_R_MASK (0x3 << 12)
579 #define RT5640_G_IN_R_SM_R_SFT 12
582 #define RT5640_G_DAC_R2_SM_R_MASK (0x3 << 8)
583 #define RT5640_G_DAC_R2_SM_R_SFT 8
604 #define RT5640_M_SV_L_SPM_L (0x1 << 12)
605 #define RT5640_M_SV_L_SPM_L_SFT 12
612 #define RT5640_M_SV_R_SPM_R (0x1 << 12)
613 #define RT5640_M_SV_R_SPM_R_SFT 12
628 #define RT5640_M_OV_L_MM (0x1 << 12)
629 #define RT5640_M_OV_L_MM_SFT 12
656 #define RT5640_M_SM_L_OM_L (0x1 << 8)
657 #define RT5640_M_SM_L_OM_L_SFT 8
696 #define RT5640_M_SM_L_OM_R (0x1 << 8)
697 #define RT5640_M_SM_L_OM_R_SFT 8
722 #define RT5640_M_OV_R_LM (0x1 << 12)
723 #define RT5640_M_OV_R_LM_SFT 12
732 #define RT5640_PWR_DAC_L1 (0x1 << 12)
733 #define RT5640_PWR_DAC_L1_BIT 12
754 #define RT5640_PWR_I2S_DSP (0x1 << 12)
755 #define RT5640_PWR_I2S_DSP_BIT 12
764 #define RT5640_PWR_LM (0x1 << 12)
765 #define RT5640_PWR_LM_BIT 12
770 #define RT5640_PWR_MA (0x1 << 8)
771 #define RT5640_PWR_MA_BIT 8
792 #define RT5640_PWR_BST4 (0x1 << 12)
793 #define RT5640_PWR_BST4_BIT 12
806 #define RT5640_PWR_SM_R (0x1 << 12)
807 #define RT5640_PWR_SM_R_BIT 12
820 #define RT5640_PWR_OV_R (0x1 << 12)
821 #define RT5640_PWR_OV_R_BIT 12
828 #define RT5640_PWR_IN_R (0x1 << 8)
829 #define RT5640_PWR_IN_R_BIT 8
836 #define RT5640_I2S_IF_MASK (0x7 << 12)
837 #define RT5640_I2S_IF_SFT 12
843 #define RT5640_I2S_I_CP_MASK (0x3 << 8)
844 #define RT5640_I2S_I_CP_SFT 8
845 #define RT5640_I2S_I_CP_OFF (0x0 << 8)
846 #define RT5640_I2S_I_CP_U_LAW (0x1 << 8)
847 #define RT5640_I2S_I_CP_A_LAW (0x2 << 8)
876 #define RT5640_I2S_PD1_MASK (0x7 << 12)
877 #define RT5640_I2S_PD1_SFT 12
878 #define RT5640_I2S_PD1_1 (0x0 << 12)
879 #define RT5640_I2S_PD1_2 (0x1 << 12)
880 #define RT5640_I2S_PD1_3 (0x2 << 12)
881 #define RT5640_I2S_PD1_4 (0x3 << 12)
882 #define RT5640_I2S_PD1_6 (0x4 << 12)
883 #define RT5640_I2S_PD1_8 (0x5 << 12)
884 #define RT5640_I2S_PD1_12 (0x6 << 12)
885 #define RT5640_I2S_PD1_16 (0x7 << 12)
890 #define RT5640_I2S_PD2_MASK (0x7 << 8)
891 #define RT5640_I2S_PD2_SFT 8
892 #define RT5640_I2S_PD2_1 (0x0 << 8)
893 #define RT5640_I2S_PD2_2 (0x1 << 8)
894 #define RT5640_I2S_PD2_3 (0x2 << 8)
895 #define RT5640_I2S_PD2_4 (0x3 << 8)
896 #define RT5640_I2S_PD2_6 (0x4 << 8)
897 #define RT5640_I2S_PD2_8 (0x5 << 8)
898 #define RT5640_I2S_PD2_12 (0x6 << 8)
899 #define RT5640_I2S_PD2_16 (0x7 << 8)
934 #define RT5640_ADC_R_OSR_MASK (0x3 << 12)
935 #define RT5640_ADC_R_OSR_SFT 12
936 #define RT5640_ADC_R_OSR_128 (0x0 << 12)
937 #define RT5640_ADC_R_OSR_64 (0x1 << 12)
938 #define RT5640_ADC_R_OSR_32 (0x2 << 12)
939 #define RT5640_ADC_R_OSR_16 (0x3 << 12)
958 #define RT5640_DMIC_1R_LH_MASK (0x1 << 12)
959 #define RT5640_DMIC_1R_LH_SFT 12
960 #define RT5640_DMIC_1R_LH_FALLING (0x0 << 12)
961 #define RT5640_DMIC_1R_LH_RISING (0x1 << 12)
974 #define RT5640_DMIC_2R_LH_MASK (0x1 << 8)
975 #define RT5640_DMIC_2R_LH_SFT 8
976 #define RT5640_DMIC_2R_LH_FALLING (0x0 << 8)
977 #define RT5640_DMIC_2R_LH_RISING (0x1 << 8)
987 #define RT5640_PLL1_SRC_MASK (0x3 << 12)
988 #define RT5640_PLL1_SRC_SFT 12
989 #define RT5640_PLL1_SRC_MCLK (0x0 << 12)
990 #define RT5640_PLL1_SRC_BCLK1 (0x1 << 12)
991 #define RT5640_PLL1_SRC_BCLK2 (0x2 << 12)
992 #define RT5640_PLL1_SRC_BCLK3 (0x3 << 12)
1010 #define RT5640_PLL_M_MASK (RT5640_PLL_M_MAX << 12)
1011 #define RT5640_PLL_M_SFT 12
1024 #define RT5640_I2S2_F_MASK (0x1 << 12)
1025 #define RT5640_I2S2_F_SFT 12
1026 #define RT5640_I2S2_F_I2S2_D2 (0x0 << 12)
1027 #define RT5640_I2S2_F_I2S1_TCLK (0x1 << 12)
1032 #define RT5640_DMIC_2_M_MASK (0x1 << 8)
1033 #define RT5640_DMIC_2_M_SFT 8
1034 #define RT5640_DMIC_2_M_NOR (0x0 << 8)
1035 #define RT5640_DMIC_2_M_ASYN (0x1 << 8)
1054 #define RT5640_MAD_R_M_MASK (0x1 << 12)
1055 #define RT5640_MAD_R_M_SFT 12
1056 #define RT5640_MAD_R_M_NOR (0x0 << 12)
1057 #define RT5640_MAD_R_M_ASYN (0x1 << 12)
1081 #define RT5640_I2S1_RATE_MASK (0xf << 12)
1082 #define RT5640_I2S1_RATE_SFT 12
1083 #define RT5640_I2S2_RATE_MASK (0xf << 8)
1084 #define RT5640_I2S2_RATE_SFT 8
1087 #define RT5640_I2S1_PD_MASK (0x7 << 12)
1088 #define RT5640_I2S1_PD_SFT 12
1089 #define RT5640_I2S2_PD_MASK (0x7 << 8)
1090 #define RT5640_I2S2_PD_SFT 8
1097 #define RT5640_HP_OC_TH_MASK (0x3 << 8)
1098 #define RT5640_HP_OC_TH_SFT 8
1099 #define RT5640_HP_OC_TH_90 (0x0 << 8)
1100 #define RT5640_HP_OC_TH_105 (0x1 << 8)
1101 #define RT5640_HP_OC_TH_120 (0x2 << 8)
1102 #define RT5640_HP_OC_TH_135 (0x3 << 8)
1109 #define RT5640_AUTO_PD_MASK (0x1 << 8)
1110 #define RT5640_AUTO_PD_SFT 8
1111 #define RT5640_AUTO_PD_DIS (0x0 << 8)
1112 #define RT5640_AUTO_PD_EN (0x1 << 8)
1117 #define RT5640_CLSD_RATIO_MASK (0xf << 12)
1118 #define RT5640_CLSD_RATIO_SFT 12
1137 #define RT5640_HP_R_SMT_MASK (0x1 << 8)
1138 #define RT5640_HP_R_SMT_SFT 8
1139 #define RT5640_HP_R_SMT_DIS (0x0 << 8)
1140 #define RT5640_HP_R_SMT_EN (0x1 << 8)
1179 #define RT5640_RAMP_MASK (0x1 << 12)
1180 #define RT5640_RAMP_SFT 12
1181 #define RT5640_RAMP_DIS (0x0 << 12)
1182 #define RT5640_RAMP_EN (0x1 << 12)
1191 #define RT5640_MRES_MASK (0x3 << 8)
1192 #define RT5640_MRES_SFT 8
1193 #define RT5640_MRES_15MO (0x0 << 8)
1194 #define RT5640_MRES_25MO (0x1 << 8)
1195 #define RT5640_MRES_35MO (0x2 << 8)
1196 #define RT5640_MRES_45MO (0x3 << 8)
1209 #define RT5640_CP_SYS_MASK (0x7 << 12)
1210 #define RT5640_CP_SYS_SFT 12
1211 #define RT5640_CP_FQ1_MASK (0x7 << 8)
1212 #define RT5640_CP_FQ1_SFT 8
1235 #define RT5640_PM_HP_MASK (0x3 << 8)
1236 #define RT5640_PM_HP_SFT 8
1237 #define RT5640_PM_HP_LV (0x0 << 8)
1238 #define RT5640_PM_HP_MV (0x1 << 8)
1239 #define RT5640_PM_HP_HV (0x2 << 8)
1270 #define RT5640_MIC2_CLK_MASK (0x1 << 12)
1271 #define RT5640_MIC2_CLK_SFT 12
1272 #define RT5640_MIC2_CLK_DIS (0x0 << 12)
1273 #define RT5640_MIC2_CLK_EN (0x1 << 12)
1283 #define RT5640_MIC2_OVCD_MASK (0x1 << 8)
1284 #define RT5640_MIC2_OVCD_SFT 8
1285 #define RT5640_MIC2_OVCD_DIS (0x0 << 8)
1286 #define RT5640_MIC2_OVCD_EN (0x1 << 8)
1312 #define RT5640_EQ_DITH_MASK (0x3 << 8)
1313 #define RT5640_EQ_DITH_SFT 8
1314 #define RT5640_EQ_DITH_NOR (0x0 << 8)
1315 #define RT5640_EQ_DITH_LSB (0x1 << 8)
1316 #define RT5640_EQ_DITH_LSB_1 (0x2 << 8)
1317 #define RT5640_EQ_DITH_LSB_2 (0x3 << 8)
1320 #define RT5640_EQ_HPF1_M_MASK (0x1 << 8)
1321 #define RT5640_EQ_HPF1_M_SFT 8
1322 #define RT5640_EQ_HPF1_M_HI (0x0 << 8)
1323 #define RT5640_EQ_HPF1_M_1ST (0x1 << 8)
1374 #define RT5640_DRC_AGC_AR_MASK (0x1f << 8)
1375 #define RT5640_DRC_AGC_AR_SFT 8
1388 #define RT5640_DRC_AGC_POB_MASK (0x3f << 8)
1389 #define RT5640_DRC_AGC_POB_SFT 8
1404 #define RT5640_DRC_AGC_NGB_MASK (0xf << 12)
1405 #define RT5640_DRC_AGC_NGB_SFT 12
1428 #define RT5640_ANC_MD_MASK (0x3 << 12)
1429 #define RT5640_ANC_MD_SFT 12
1430 #define RT5640_ANC_MD_DIS (0x0 << 12)
1431 #define RT5640_ANC_MD_67MS (0x1 << 12)
1432 #define RT5640_ANC_MD_267MS (0x2 << 12)
1433 #define RT5640_ANC_MD_1067MS (0x3 << 12)
1442 #define RT5640_ANC_ZCD_MASK (0x3 << 8)
1443 #define RT5640_ANC_ZCD_SFT 8
1444 #define RT5640_ANC_ZCD_DIS (0x0 << 8)
1445 #define RT5640_ANC_ZCD_T1 (0x1 << 8)
1446 #define RT5640_ANC_ZCD_T2 (0x2 << 8)
1447 #define RT5640_ANC_ZCD_WT (0x3 << 8)
1460 #define RT5640_ANC_FG_R_MASK (0xf << 12)
1461 #define RT5640_ANC_FG_R_SFT 12
1462 #define RT5640_ANC_FG_L_MASK (0xf << 8)
1463 #define RT5640_ANC_FG_L_SFT 8
1499 #define RT5640_JD_SPL_TRG_MASK (0x1 << 8)
1500 #define RT5640_JD_SPL_TRG_SFT 8
1501 #define RT5640_JD_SPL_TRG_LO (0x0 << 8)
1502 #define RT5640_JD_SPL_TRG_HI (0x1 << 8)
1571 #define RT5640_OT_STKY_MASK (0x1 << 12)
1572 #define RT5640_OT_STKY_SFT 12
1573 #define RT5640_OT_STKY_DIS (0x0 << 12)
1574 #define RT5640_OT_STKY_EN (0x1 << 12)
1615 #define RT5640_GPIO1_STATUS (0x1 << 8)
1630 #define RT5640_GP3_PIN_MASK (0x3 << 12)
1631 #define RT5640_GP3_PIN_SFT 12
1632 #define RT5640_GP3_PIN_GPIO3 (0x0 << 12)
1633 #define RT5640_GP3_PIN_DMIC1_SDA (0x1 << 12)
1634 #define RT5640_GP3_PIN_IRQ (0x2 << 12)
1661 #define RT5640_GP3_PF_MASK (0x1 << 8)
1662 #define RT5640_GP3_PF_SFT 8
1663 #define RT5640_GP3_PF_IN (0x0 << 8)
1664 #define RT5640_GP3_PF_OUT (0x1 << 8)
1698 /* FM34-500 Register Control 1 (0xc4) */
1701 /* FM34-500 Register Control 2 (0xc5) */
1704 /* FM34-500 Register Control 3 (0xc6) */
1711 #define RT5640_DSP_CLK_MASK (0x3 << 12)
1712 #define RT5640_DSP_CLK_SFT 12
1713 #define RT5640_DSP_CLK_384K (0x0 << 12)
1714 #define RT5640_DSP_CLK_192K (0x1 << 12)
1715 #define RT5640_DSP_CLK_96K (0x2 << 12)
1716 #define RT5640_DSP_CLK_64K (0x3 << 12)
1727 #define RT5640_DSP_W_EN (0x1 << 8)
1728 #define RT5640_DSP_W_EN_BIT 8
1737 #define RT5640_REG_SEQ_MASK (0xf << 12)
1738 #define RT5640_REG_SEQ_SFT 12
1751 #define RT5640_SEQ_2_PT_MASK (0x1 << 8)
1752 #define RT5640_SEQ_2_PT_BIT 8
1761 #define RT5640_SEQ_DLY_MASK (0xff << 8)
1762 #define RT5640_SEQ_DLY_SFT 8
1773 #define RT5640_SEQ1_START_MASK (0xf << 8)
1774 #define RT5640_SEQ1_START_SFT 8
1779 #define RT5640_SEQ2_START_MASK (0xf << 8)
1780 #define RT5640_SEQ2_START_SFT 8
1803 #define RT5640_BB_CT_MASK (0x7 << 12)
1804 #define RT5640_BB_CT_SFT 12
1805 #define RT5640_BB_CT_A (0x0 << 12)
1806 #define RT5640_BB_CT_B (0x1 << 12)
1807 #define RT5640_BB_CT_C (0x2 << 12)
1808 #define RT5640_BB_CT_D (0x3 << 12)
1811 #define RT5640_M_BB_R_MASK (0x1 << 8)
1812 #define RT5640_M_BB_R_SFT 8
1829 #define RT5640_EG_MP3_MASK (0x1f << 8)
1830 #define RT5640_EG_MP3_SFT 8
1845 #define RT5640_OG_MP3_MASK (0x1f << 8)
1846 #define RT5640_OG_MP3_SFT 8
1871 #define RT5640_M_3D_D2H_MASK (0x1 << 8)
1872 #define RT5640_M_3D_D2H_SFT 8
1883 #define RT5640_HPF_CF_L_MASK (0x7 << 12)
1884 #define RT5640_HPF_CF_L_SFT 12
1889 #define RT5640_HPF_CF_R_MASK (0x7 << 8)
1890 #define RT5640_HPF_CF_R_SFT 8
1950 #define RT5640_HP_SV_MASK (0x1 << 12)
1951 #define RT5640_HP_SV_SFT 12
1952 #define RT5640_HP_SV_DIS (0x0 << 12)
1953 #define RT5640_HP_SV_EN (0x1 << 12)
1965 #define RT5640_M_ZCD_RM_R (0x1 << 8)
1982 #define RT5640_M_MONO_ADC_R (0x1 << 12)
1983 #define RT5640_M_MONO_ADC_R_SFT 12
1989 #define RT5640_MIC_OVCD_SF_MASK (0x3 << 8)
1990 #define RT5640_MIC_OVCD_SF_SFT 8
1991 #define RT5640_MIC_OVCD_SF_0P5 (0x0 << 8)
1992 #define RT5640_MIC_OVCD_SF_0P75 (0x1 << 8)
1993 #define RT5640_MIC_OVCD_SF_1P0 (0x2 << 8)
1994 #define RT5640_MIC_OVCD_SF_1P5 (0x3 << 8)
2003 #define RT5640_3D_SPK_CG_MASK (0x1f << 8)
2004 #define RT5640_3D_SPK_CG_SFT 8
2034 /* Wind Noise Detection Control 8 (0x73) */
2035 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2037 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2038 #define RT5640_WND_STRONG_SFT 12