Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
19 /* I/O - Output */
24 /* I/O - Input */
32 /* I/O - ADC/DAC/DMIC */
40 /* Mixer - D-D */
49 /* Mixer - PDM */
51 /* Mixer - ADC */
56 /* Mixer - DAC */
94 /* Format - ADC/DAC */
101 /* Format - TDM Control */
107 /* Function - Analog */
123 /* Function - Digital */
227 #define RT5645_L_VOL_MASK (0x3f << 8)
228 #define RT5645_L_VOL_SFT 8
233 #define RT5645_CBJ_BST1_MASK (0xf << 12)
234 #define RT5645_CBJ_BST1_SFT (12)
236 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
244 #define RT5645_CBJ_MN_JD (0x1 << 12)
253 #define RT5645_BST_MASK1 (0xf<<12)
254 #define RT5645_BST_SFT1 12
255 #define RT5645_BST_MASK2 (0xf<<8)
256 #define RT5645_BST_SFT2 8
265 #define RT5645_INL_VOL_MASK (0x1f << 8)
266 #define RT5645_INL_VOL_SFT 8
275 #define RT5645_DAC_L1_VOL_MASK (0xff << 8)
276 #define RT5645_DAC_L1_VOL_SFT 8
281 #define RT5645_DAC_L2_VOL_MASK (0xff << 8)
282 #define RT5645_DAC_L2_VOL_SFT 8
289 #define RT5645_M_DAC_R2_VOL (0x1 << 12)
290 #define RT5645_M_DAC_R2_VOL_SFT 12
297 #define RT5645_ADC_L_VOL_MASK (0x7f << 8)
298 #define RT5645_ADC_L_VOL_SFT 8
303 #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
304 #define RT5645_MONO_ADC_L_VOL_SFT 8
311 #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
312 #define RT5645_STO1_ADC_R_BST_SFT 12
319 #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)
320 #define RT5645_MONO_ADC_R_BST_SFT 12
333 #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
334 #define RT5645_ADC_1_SRC_SFT 12
335 #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
336 #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
339 #define RT5645_DMIC_SRC_MASK (0x1 << 8)
340 #define RT5645_DMIC_SRC_SFT 8
353 #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
354 #define RT5645_MONO_ADC_L1_SRC_SFT 12
355 #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
356 #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
359 #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
360 #define RT5645_MONO_DMIC_L_SRC_SFT 8
385 #define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
386 #define RT5645_DAC1_L_SEL_SFT 8
387 #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
388 #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
389 #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
390 #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
401 #define RT5645_M_DAC_L2 (0x1 << 12)
402 #define RT5645_M_DAC_L2_SFT 12
409 #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
410 #define RT5645_DAC_R1_STO_L_VOL_SFT 8
431 #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
432 #define RT5645_M_DAC_L2_MONO_L_SFT 12
459 #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
460 #define RT5645_DAC_L2_DAC_L_VOL_SFT 12
467 #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
468 #define RT5645_DAC_R2_DAC_R_VOL_SFT 8
487 #define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
488 #define RT5645_IF2_ADC_IN_SFT 12
491 #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
492 #define RT5645_IF2_ADC_SEL_SFT 8
507 #define RT5645_M_PDM1_R (0x1 << 12)
508 #define RT5645_M_PDM1_R_SFT 12
515 #define RT5645_M_PDM2_R (0x1 << 8)
516 #define RT5645_M_PDM2_R_SFT 8
606 #define RT5645_IRQ_PSV_MODE (0x1 << 12)
611 #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
612 #define RT5645_G_IN_L_SM_L_SFT 12
615 #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
616 #define RT5645_G_DAC_L2_SM_L_SFT 8
633 #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
634 #define RT5645_G_IN_R_SM_R_SFT 12
637 #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
638 #define RT5645_G_DAC_R2_SM_R_SFT 8
659 #define RT5645_M_SV_R_SPM_L (0x1 << 12)
660 #define RT5645_M_SV_R_SPM_L_SFT 12
679 #define RT5645_M_DAC_L2_MA (0x1 << 8)
680 #define RT5645_M_DAC_L2_MA_SFT 8
763 #define RT5645_M_OV_R_LM (0x1 << 12)
764 #define RT5645_M_OV_R_LM_SFT 12
775 #define RT5645_PWR_DAC_L1 (0x1 << 12)
776 #define RT5645_PWR_DAC_L1_BIT 12
781 #define RT5645_PWR_CLS_D_L (0x1 << 8)
782 #define RT5645_PWR_CLS_D_L_BIT 8
801 #define RT5645_PWR_I2S_DSP (0x1 << 12)
802 #define RT5645_PWR_I2S_DSP_BIT 12
825 #define RT5645_PWR_LM (0x1 << 12)
826 #define RT5645_PWR_LM_BIT 12
851 #define RT5645_PWR_BST4 (0x1 << 12)
852 #define RT5645_PWR_BST4_BIT 12
877 #define RT5645_PWR_SM_R (0x1 << 12)
878 #define RT5645_PWR_SM_R_BIT 12
883 #define RT5645_PWR_MM (0x1 << 8)
884 #define RT5645_PWR_MM_BIT 8
903 #define RT5645_PWR_IN_R (0x1 << 8)
904 #define RT5645_PWR_IN_R_BIT 8
918 #define RT5645_I2S_I_CP_MASK (0x3 << 8)
919 #define RT5645_I2S_I_CP_SFT 8
920 #define RT5645_I2S_I_CP_OFF (0x0 << 8)
921 #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
922 #define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
947 #define RT5645_I2S_PD1_MASK (0x7 << 12)
948 #define RT5645_I2S_PD1_SFT 12
949 #define RT5645_I2S_PD1_1 (0x0 << 12)
950 #define RT5645_I2S_PD1_2 (0x1 << 12)
951 #define RT5645_I2S_PD1_3 (0x2 << 12)
952 #define RT5645_I2S_PD1_4 (0x3 << 12)
953 #define RT5645_I2S_PD1_6 (0x4 << 12)
954 #define RT5645_I2S_PD1_8 (0x5 << 12)
955 #define RT5645_I2S_PD1_12 (0x6 << 12)
956 #define RT5645_I2S_PD1_16 (0x7 << 12)
961 #define RT5645_I2S_PD2_MASK (0x7 << 8)
962 #define RT5645_I2S_PD2_SFT 8
963 #define RT5645_I2S_PD2_1 (0x0 << 8)
964 #define RT5645_I2S_PD2_2 (0x1 << 8)
965 #define RT5645_I2S_PD2_3 (0x2 << 8)
966 #define RT5645_I2S_PD2_4 (0x3 << 8)
967 #define RT5645_I2S_PD2_6 (0x4 << 8)
968 #define RT5645_I2S_PD2_8 (0x5 << 8)
969 #define RT5645_I2S_PD2_12 (0x6 << 8)
970 #define RT5645_I2S_PD2_16 (0x7 << 8)
1005 #define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1006 #define RT5645_ADC_R_OSR_SFT 12
1007 #define RT5645_ADC_R_OSR_128 (0x0 << 12)
1008 #define RT5645_ADC_R_OSR_64 (0x1 << 12)
1009 #define RT5645_ADC_R_OSR_32 (0x2 << 12)
1010 #define RT5645_ADC_R_OSR_16 (0x3 << 12)
1029 #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1030 #define RT5645_DMIC_1R_LH_SFT 12
1031 #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1032 #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1043 #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1044 #define RT5645_DMIC_2R_LH_SFT 8
1045 #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1046 #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1060 #define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1061 #define RT5645_IF1_ADC_IN_SFT 8
1093 #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1094 #define RT5645_PLL_M_SFT 12
1107 #define RT5645_I2S2_F_MASK (0x1 << 12)
1108 #define RT5645_I2S2_F_SFT 12
1109 #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1110 #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1115 #define RT5645_DMIC_2_M_MASK (0x1 << 8)
1116 #define RT5645_DMIC_2_M_SFT 8
1117 #define RT5645_DMIC_2_M_NOR (0x0 << 8)
1118 #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1127 #define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
1128 #define RT5645_DA_STO_CLK_SEL_SFT 12
1129 #define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1130 #define RT5645_DA_MONOL_CLK_SEL_SFT 8
1143 #define RT5645_I2S1_PD_MASK (0x7 << 12)
1144 #define RT5645_I2S1_PD_SFT 12
1145 #define RT5645_I2S2_PD_MASK (0x7 << 8)
1146 #define RT5645_I2S2_PD_SFT 8
1153 #define RT5645_HP_OC_TH_MASK (0x3 << 8)
1154 #define RT5645_HP_OC_TH_SFT 8
1155 #define RT5645_HP_OC_TH_90 (0x0 << 8)
1156 #define RT5645_HP_OC_TH_105 (0x1 << 8)
1157 #define RT5645_HP_OC_TH_120 (0x2 << 8)
1158 #define RT5645_HP_OC_TH_135 (0x3 << 8)
1165 #define RT5645_AUTO_PD_MASK (0x1 << 8)
1166 #define RT5645_AUTO_PD_SFT 8
1167 #define RT5645_AUTO_PD_DIS (0x0 << 8)
1168 #define RT5645_AUTO_PD_EN (0x1 << 8)
1173 #define RT5645_CLSD_RATIO_MASK (0xf << 12)
1174 #define RT5645_CLSD_RATIO_SFT 12
1193 #define RT5645_HP_R_SMT_MASK (0x1 << 8)
1194 #define RT5645_HP_R_SMT_SFT 8
1195 #define RT5645_HP_R_SMT_DIS (0x0 << 8)
1196 #define RT5645_HP_R_SMT_EN (0x1 << 8)
1235 #define RT5645_RAMP_MASK (0x1 << 12)
1236 #define RT5645_RAMP_SFT 12
1237 #define RT5645_RAMP_DIS (0x0 << 12)
1238 #define RT5645_RAMP_EN (0x1 << 12)
1247 #define RT5645_MRES_MASK (0x3 << 8)
1248 #define RT5645_MRES_SFT 8
1249 #define RT5645_MRES_15MO (0x0 << 8)
1250 #define RT5645_MRES_25MO (0x1 << 8)
1251 #define RT5645_MRES_35MO (0x2 << 8)
1252 #define RT5645_MRES_45MO (0x3 << 8)
1265 #define RT5645_CP_SYS_MASK (0x7 << 12)
1266 #define RT5645_CP_SYS_SFT 12
1267 #define RT5645_CP_FQ1_MASK (0x7 << 8)
1268 #define RT5645_CP_FQ1_SFT 8
1305 #define RT5645_MIC2_CLK_MASK (0x1 << 12)
1306 #define RT5645_MIC2_CLK_SFT 12
1307 #define RT5645_MIC2_CLK_DIS (0x0 << 12)
1308 #define RT5645_MIC2_CLK_EN (0x1 << 12)
1318 #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1319 #define RT5645_MIC2_OVCD_SFT 8
1320 #define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1321 #define RT5645_MIC2_OVCD_EN (0x1 << 8)
1343 #define RT5645_VAD_SEL_MASK (0x3 << 8)
1344 #define RT5645_VAD_SEL_SFT 8
1357 #define RT5645_EQ_DITH_MASK (0x3 << 8)
1358 #define RT5645_EQ_DITH_SFT 8
1359 #define RT5645_EQ_DITH_NOR (0x0 << 8)
1360 #define RT5645_EQ_DITH_LSB (0x1 << 8)
1361 #define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1362 #define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1365 #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1366 #define RT5645_EQ_HPF1_M_SFT 8
1367 #define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1368 #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1420 #define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1421 #define RT5645_DRC_AGC_AR_SFT 8
1434 #define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1435 #define RT5645_DRC_AGC_POB_SFT 8
1450 #define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1451 #define RT5645_DRC_AGC_NGB_SFT 12
1474 #define RT5645_ANC_MD_MASK (0x3 << 12)
1475 #define RT5645_ANC_MD_SFT 12
1476 #define RT5645_ANC_MD_DIS (0x0 << 12)
1477 #define RT5645_ANC_MD_67MS (0x1 << 12)
1478 #define RT5645_ANC_MD_267MS (0x2 << 12)
1479 #define RT5645_ANC_MD_1067MS (0x3 << 12)
1488 #define RT5645_ANC_ZCD_MASK (0x3 << 8)
1489 #define RT5645_ANC_ZCD_SFT 8
1490 #define RT5645_ANC_ZCD_DIS (0x0 << 8)
1491 #define RT5645_ANC_ZCD_T1 (0x1 << 8)
1492 #define RT5645_ANC_ZCD_T2 (0x2 << 8)
1493 #define RT5645_ANC_ZCD_WT (0x3 << 8)
1506 #define RT5645_ANC_FG_R_MASK (0xf << 12)
1507 #define RT5645_ANC_FG_R_SFT 12
1508 #define RT5645_ANC_FG_L_MASK (0xf << 8)
1509 #define RT5645_ANC_FG_L_SFT 8
1545 #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1546 #define RT5645_JD_SPL_TRG_SFT 8
1547 #define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1548 #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1617 #define RT5645_OT_STKY_MASK (0x1 << 12)
1618 #define RT5645_OT_STKY_SFT 12
1619 #define RT5645_OT_STKY_DIS (0x0 << 12)
1620 #define RT5645_OT_STKY_EN (0x1 << 12)
1648 #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1649 #define RT5645_MB2_OC_STKY_SFT 12
1650 #define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1651 #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1674 #define RT5645_GP3_PIN_MASK (0x3 << 12)
1675 #define RT5645_GP3_PIN_SFT 12
1676 #define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1677 #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1678 #define RT5645_GP3_PIN_IRQ (0x2 << 12)
1691 #define RT5645_I2S2_SEL (0x1 << 8)
1692 #define RT5645_I2S2_SEL_SFT 8
1735 #define RT5645_GP3_PF_MASK (0x1 << 8)
1736 #define RT5645_GP3_PF_SFT 8
1737 #define RT5645_GP3_PF_IN (0x0 << 8)
1738 #define RT5645_GP3_PF_OUT (0x1 << 8)
1773 #define RT5645_REG_SEQ_MASK (0xf << 12)
1774 #define RT5645_REG_SEQ_SFT 12
1787 #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1788 #define RT5645_SEQ_2_PT_BIT 8
1797 #define RT5645_SEQ_DLY_MASK (0xff << 8)
1798 #define RT5645_SEQ_DLY_SFT 8
1809 #define RT5645_SEQ1_START_MASK (0xf << 8)
1810 #define RT5645_SEQ1_START_SFT 8
1815 #define RT5645_SEQ2_START_MASK (0xf << 8)
1816 #define RT5645_SEQ2_START_SFT 8
1839 #define RT5645_BB_CT_MASK (0x7 << 12)
1840 #define RT5645_BB_CT_SFT 12
1841 #define RT5645_BB_CT_A (0x0 << 12)
1842 #define RT5645_BB_CT_B (0x1 << 12)
1843 #define RT5645_BB_CT_C (0x2 << 12)
1844 #define RT5645_BB_CT_D (0x3 << 12)
1847 #define RT5645_M_BB_R_MASK (0x1 << 8)
1848 #define RT5645_M_BB_R_SFT 8
1866 #define RT5645_EG_MP3_MASK (0x1f << 8)
1867 #define RT5645_EG_MP3_SFT 8
1882 #define RT5645_OG_MP3_MASK (0x1f << 8)
1883 #define RT5645_OG_MP3_SFT 8
1908 #define RT5645_M_3D_D2H_MASK (0x1 << 8)
1909 #define RT5645_M_3D_D2H_SFT 8
1920 #define RT5645_HPF_CF_L_MASK (0x7 << 12)
1921 #define RT5645_HPF_CF_L_SFT 12
1926 #define RT5645_HPF_CF_R_MASK (0x7 << 8)
1927 #define RT5645_HPF_CF_R_SFT 8
1987 #define RT5645_HP_SV_MASK (0x1 << 12)
1988 #define RT5645_HP_SV_SFT 12
1989 #define RT5645_HP_SV_DIS (0x0 << 12)
1990 #define RT5645_HP_SV_EN (0x1 << 12)
2002 #define RT5645_M_ZCD_RM_R (0x1 << 8)
2028 #define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2029 #define RT5645_3D_SPK_CG_SFT 8
2059 /* Wind Noise Detection Control 8 (0x73) */
2060 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2062 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2063 #define RT5645_WND_STRONG_SFT 12
2087 #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2104 #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2105 #define RT5645_IF1_ADC1_IN1_SFT 12
2129 #define RT5645_JD_PSV_MODE (0x1 << 12)