Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5668.h -- RT5668/RT5658 ALSA SoC audio driver
21 /* I/O - Output */
29 /* I/O - Input */
38 /* I/O - ADC/DAC/DMIC */
44 /* Mixer - D-D */
51 /* Mixer - ADC */
70 /* Format - ADC/DAC */
77 /* Format - TDM Control */
83 /* Function - Analog */
111 /* Function - Digital */
367 #define RT5668_L_VOL_MASK (0x3f << 8)
368 #define RT5668_L_VOL_SFT 8
373 #define RT5668_G_HP (0xf << 8)
374 #define RT5668_G_HP_SFT 8
379 #define RT5668_BST_CBJ_MASK (0xf << 8)
380 #define RT5668_BST_CBJ_SFT 8
388 #define RT5668_DET_TYPE (0x1 << 12)
389 #define RT5668_DET_TYPE_SFT 12
394 #define RT5668_POL_FAST_OFF_MASK (0x1 << 8)
395 #define RT5668_POL_FAST_OFF_HIGH (0x1 << 8)
396 #define RT5668_POL_FAST_OFF_LOW (0x0 << 8)
433 #define RT5668_SEL_SHT_MID_TON_MASK (0x3 << 12)
434 #define RT5668_SEL_SHT_MID_TON_2 (0x0 << 12)
435 #define RT5668_SEL_SHT_MID_TON_3 (0x1 << 12)
441 #define RT5668_DAC_L1_VOL_MASK (0xff << 8)
442 #define RT5668_DAC_L1_VOL_SFT 8
447 #define RT5668_ADC_L_VOL_MASK (0x7f << 8)
448 #define RT5668_ADC_L_VOL_SFT 8
455 #define RT5668_STO1_ADC_R_BST_MASK (0x3 << 12)
456 #define RT5668_STO1_ADC_R_BST_SFT 12
459 #define RT5668_ST_SRC_SEL (0x1 << 8)
460 #define RT5668_ST_SRC_SFT 8
475 #define RT5668_STO1_ADC2L_SRC_MASK (0x1 << 12)
476 #define RT5668_STO1_ADC2L_SRC_SFT 12
481 #define RT5668_STO1_DMIC_SRC_MASK (0x1 << 8)
482 #define RT5668_STO1_DMIC_SRC_SFT 8
483 #define RT5668_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
484 #define RT5668_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
503 #define RT5668_DAC1_L_SEL_MASK (0x1 << 8)
504 #define RT5668_DAC1_L_SEL_SFT 8
517 #define RT5668_G_DAC_R1_STO_L_MASK (0x1 << 12)
518 #define RT5668_G_DAC_R1_STO_L_SFT 12
531 #define RT5668_M_ST_STO_R (0x1 << 8)
532 #define RT5668_M_ST_STO_R_SFT 8
557 #define RT5668_PWR_LDO (0x1 << 8)
558 #define RT5668_PWR_LDO_BIT 8
580 #define RT5668_PWR_FV2 (0x1 << 12)
581 #define RT5668_PWR_FV2_BIT 12
646 #define RT5668_POW_CLK_DET2_SFT 8
666 #define RT5668_I2S1_TX_CHL_MASK (0x7 << 12)
667 #define RT5668_I2S1_TX_CHL_SFT 12
668 #define RT5668_I2S1_TX_CHL_16 (0x0 << 12)
669 #define RT5668_I2S1_TX_CHL_20 (0x1 << 12)
670 #define RT5668_I2S1_TX_CHL_24 (0x2 << 12)
671 #define RT5668_I2S1_TX_CHL_32 (0x3 << 12)
672 #define RT5668_I2S1_TX_CHL_8 (0x4 << 12)
673 #define RT5668_I2S1_RX_CHL_MASK (0x7 << 8)
674 #define RT5668_I2S1_RX_CHL_SFT 8
675 #define RT5668_I2S1_RX_CHL_16 (0x0 << 8)
676 #define RT5668_I2S1_RX_CHL_20 (0x1 << 8)
677 #define RT5668_I2S1_RX_CHL_24 (0x2 << 8)
678 #define RT5668_I2S1_RX_CHL_32 (0x3 << 8)
679 #define RT5668_I2S1_RX_CHL_8 (0x4 << 8)
707 #define RT5668_I2S_BP_MASK (0x1 << 8)
708 #define RT5668_I2S_BP_SFT 8
709 #define RT5668_I2S_BP_NOR (0x0 << 8)
710 #define RT5668_I2S_BP_INV (0x1 << 8)
729 #define RT5668_ADC_OSR_MASK (0xf << 12)
730 #define RT5668_ADC_OSR_SFT 12
731 #define RT5668_ADC_OSR_D_1 (0x0 << 12)
732 #define RT5668_ADC_OSR_D_2 (0x1 << 12)
733 #define RT5668_ADC_OSR_D_4 (0x2 << 12)
734 #define RT5668_ADC_OSR_D_6 (0x3 << 12)
735 #define RT5668_ADC_OSR_D_8 (0x4 << 12)
736 #define RT5668_ADC_OSR_D_12 (0x5 << 12)
737 #define RT5668_ADC_OSR_D_16 (0x6 << 12)
738 #define RT5668_ADC_OSR_D_24 (0x7 << 12)
739 #define RT5668_ADC_OSR_D_32 (0x8 << 12)
740 #define RT5668_ADC_OSR_D_48 (0x9 << 12)
741 #define RT5668_I2S_M_DIV_MASK (0xf << 12)
742 #define RT5668_I2S_M_DIV_SFT 8
743 #define RT5668_I2S_M_D_1 (0x0 << 8)
744 #define RT5668_I2S_M_D_2 (0x1 << 8)
745 #define RT5668_I2S_M_D_3 (0x2 << 8)
746 #define RT5668_I2S_M_D_4 (0x3 << 8)
747 #define RT5668_I2S_M_D_6 (0x4 << 8)
748 #define RT5668_I2S_M_D_8 (0x5 << 8)
749 #define RT5668_I2S_M_D_12 (0x6 << 8)
750 #define RT5668_I2S_M_D_16 (0x7 << 8)
751 #define RT5668_I2S_M_D_24 (0x8 << 8)
752 #define RT5668_I2S_M_D_32 (0x9 << 8)
753 #define RT5668_I2S_M_D_48 (0x10 << 8)
782 #define RT5668_TDM_TX_CH_MASK (0x3 << 12)
783 #define RT5668_TDM_TX_CH_2 (0x0 << 12)
784 #define RT5668_TDM_TX_CH_4 (0x1 << 12)
785 #define RT5668_TDM_TX_CH_6 (0x2 << 12)
786 #define RT5668_TDM_TX_CH_8 (0x3 << 12)
787 #define RT5668_TDM_RX_CH_MASK (0x3 << 8)
788 #define RT5668_TDM_RX_CH_2 (0x0 << 8)
789 #define RT5668_TDM_RX_CH_4 (0x1 << 8)
790 #define RT5668_TDM_RX_CH_6 (0x2 << 8)
791 #define RT5668_TDM_RX_CH_8 (0x3 << 8)
798 #define RT5668_IF1_ADC2_SEL_SFT 12
800 #define RT5668_IF1_ADC4_SEL_SFT 8
852 #define RT5668_PLL2_SRC_MASK (0x3 << 8)
853 #define RT5668_PLL2_SRC_SFT 8
854 #define RT5668_PLL2_SRC_MCLK (0x0 << 8)
855 #define RT5668_PLL2_SRC_BCLK1 (0x1 << 8)
856 #define RT5668_PLL2_SRC_SDW (0x2 << 8)
857 #define RT5668_PLL2_SRC_RC (0x3 << 8)
873 #define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
874 #define RT5668_PLL_M_SFT 12
883 #define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
884 #define RT5668_DAC_STO1_ASRC_SFT 12
885 #define RT5668_AD_ASRC_MASK (0x1 << 8)
886 #define RT5668_AD_ASRC_SFT 8
897 #define RT5668_FILTER_CLK_SEL_MASK (0x7 << 12)
898 #define RT5668_FILTER_CLK_SEL_SFT 12
903 #define RT5668_ASRCIN_FTK_N2_MASK (0x3 << 12)
904 #define RT5668_ASRCIN_FTK_N2_SFT 12
905 #define RT5668_ASRCIN_FTK_M1_MASK (0x7 << 8)
906 #define RT5668_ASRCIN_FTK_M1_SFT 8
911 #define RT5668_PLL2_OUT_MASK (0x1 << 8)
912 #define RT5668_PLL2_OUT_98M (0x0 << 8)
913 #define RT5668_PLL2_OUT_49M (0x1 << 8)
956 #define RT5668_RAMP_MASK (0x1 << 12)
957 #define RT5668_RAMP_SFT 12
958 #define RT5668_RAMP_DIS (0x0 << 12)
959 #define RT5668_RAMP_EN (0x1 << 12)
982 #define RT5668_PM_HP_MASK (0x3 << 8)
983 #define RT5668_PM_HP_SFT 8
984 #define RT5668_PM_HP_LV (0x0 << 8)
985 #define RT5668_PM_HP_MV (0x1 << 8)
986 #define RT5668_PM_HP_HV (0x2 << 8)
1005 #define RT5668_MIC1_OVCD_MASK (0x1 << 12)
1006 #define RT5668_MIC1_OVCD_SFT 12
1007 #define RT5668_MIC1_OVCD_DIS (0x0 << 12)
1008 #define RT5668_MIC1_OVCD_EN (0x1 << 12)
1015 #define RT5668_MIC2_OV_MASK (0x3 << 8)
1016 #define RT5668_MIC2_OV_SFT 8
1017 #define RT5668_MIC2_OV_2V7 (0x0 << 8)
1018 #define RT5668_MIC2_OV_2V4 (0x1 << 8)
1019 #define RT5668_MIC2_OV_2V25 (0x3 << 8)
1020 #define RT5668_MIC2_OV_1V8 (0x4 << 8)
1041 #define RT5668_PWR_CLK1M_MASK (0x1 << 8)
1042 #define RT5668_PWR_CLK1M_SFT 8
1043 #define RT5668_PWR_CLK1M_PD (0x0 << 8)
1044 #define RT5668_PWR_CLK1M_PU (0x1 << 8)
1050 #define RT5668_POW_ANA (0x1 << 12)
1100 #define RT5668_GP2_PIN_MASK (0x3 << 12)
1101 #define RT5668_GP2_PIN_SFT 12
1102 #define RT5668_GP2_PIN_GPIO2 (0x0 << 12)
1103 #define RT5668_GP2_PIN_LRCK2 (0x1 << 12)
1104 #define RT5668_GP2_PIN_DMIC_SDA (0x2 << 12)
1110 #define RT5668_GP4_PIN_MASK (0x3 << 8)
1111 #define RT5668_GP4_PIN_SFT 8
1112 #define RT5668_GP4_PIN_GPIO4 (0x0 << 8)
1113 #define RT5668_GP4_PIN_ADCDAT1 (0x1 << 8)
1114 #define RT5668_GP4_PIN_DMIC_CLK (0x2 << 8)
1115 #define RT5668_GP4_PIN_ADCDAT2 (0x3 << 8)
1136 #define RT5668_GP2_OUT_MASK (0x1 << 12)
1137 #define RT5668_GP2_OUT_L (0x0 << 12)
1138 #define RT5668_GP2_OUT_H (0x1 << 12)
1148 #define RT5668_GP4_OUT_MASK (0x1 << 8)
1149 #define RT5668_GP4_OUT_L (0x0 << 8)
1150 #define RT5668_GP4_OUT_H (0x1 << 8)
1211 #define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
1212 #define RT5668_CKGEN_DAC1_SFT 12
1217 #define RT5668_CKGEN_ADC1_MASK (0x1 << 12)
1218 #define RT5668_CKGEN_ADC1_SFT 12
1248 #define RT5668_SAR_POW_MASK (0x1 << 12)
1249 #define RT5668_SAR_POW_EN (0x1 << 12)
1250 #define RT5668_SAR_POW_DIS (0x0 << 12)
1260 #define RT5668_SAR_SEL_MB2_MASK (0x1 << 8)
1261 #define RT5668_SAR_SEL_MB2_SEL (0x1 << 8)
1262 #define RT5668_SAR_SEL_MB2_NOSEL (0x0 << 8)