Lines Matching +full:8 +full:- +full:12
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver
16 #include <linux/clk-provider.h>
27 /* I/O - Output */
35 /* I/O - Input */
44 /* I/O - ADC/DAC/DMIC */
50 /* Mixer - D-D */
57 /* Mixer - ADC */
76 /* Format - ADC/DAC */
83 /* Format - TDM Control */
89 /* Function - Analog */
117 /* Function - Digital */
373 #define RT5682_L_VOL_MASK (0x3f << 8)
374 #define RT5682_L_VOL_SFT 8
379 #define RT5682_G_HP (0xf << 8)
380 #define RT5682_G_HP_SFT 8
385 #define RT5682_BST_CBJ_MASK (0xf << 8)
386 #define RT5682_BST_CBJ_SFT 8
394 #define RT5682_DET_TYPE (0x1 << 12)
395 #define RT5682_DET_TYPE_SFT 12
400 #define RT5682_POL_FAST_OFF_MASK (0x1 << 8)
401 #define RT5682_POL_FAST_OFF_HIGH (0x1 << 8)
402 #define RT5682_POL_FAST_OFF_LOW (0x0 << 8)
439 #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12)
440 #define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12)
441 #define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12)
447 #define RT5682_DAC_L1_VOL_MASK (0xff << 8)
448 #define RT5682_DAC_L1_VOL_SFT 8
453 #define RT5682_ADC_L_VOL_MASK (0x7f << 8)
454 #define RT5682_ADC_L_VOL_SFT 8
461 #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12)
462 #define RT5682_STO1_ADC_R_BST_SFT 12
465 #define RT5682_ST_SRC_SEL (0x1 << 8)
466 #define RT5682_ST_SRC_SFT 8
481 #define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12)
482 #define RT5682_STO1_ADC2L_SRC_SFT 12
487 #define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8)
488 #define RT5682_STO1_DMIC_SRC_SFT 8
489 #define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
490 #define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
509 #define RT5682_DAC1_L_SEL_MASK (0x1 << 8)
510 #define RT5682_DAC1_L_SEL_SFT 8
523 #define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12)
524 #define RT5682_G_DAC_R1_STO_L_SFT 12
537 #define RT5682_M_ST_STO_R (0x1 << 8)
538 #define RT5682_M_ST_STO_R_SFT 8
563 #define RT5682_PWR_LDO (0x1 << 8)
564 #define RT5682_PWR_LDO_BIT 8
586 #define RT5682_PWR_FV2 (0x1 << 12)
587 #define RT5682_PWR_FV2_BIT 12
652 #define RT5682_POW_CLK_DET2_SFT 8
660 #define RT5682_FIFO_CLK_DIV_MASK (0x7 << 12)
661 #define RT5682_FIFO_CLK_DIV_2 (0x1 << 12)
674 #define RT5682_I2S1_TX_CHL_MASK (0x7 << 12)
675 #define RT5682_I2S1_TX_CHL_SFT 12
676 #define RT5682_I2S1_TX_CHL_16 (0x0 << 12)
677 #define RT5682_I2S1_TX_CHL_20 (0x1 << 12)
678 #define RT5682_I2S1_TX_CHL_24 (0x2 << 12)
679 #define RT5682_I2S1_TX_CHL_32 (0x3 << 12)
680 #define RT5682_I2S1_TX_CHL_8 (0x4 << 12)
681 #define RT5682_I2S1_RX_CHL_MASK (0x7 << 8)
682 #define RT5682_I2S1_RX_CHL_SFT 8
683 #define RT5682_I2S1_RX_CHL_16 (0x0 << 8)
684 #define RT5682_I2S1_RX_CHL_20 (0x1 << 8)
685 #define RT5682_I2S1_RX_CHL_24 (0x2 << 8)
686 #define RT5682_I2S1_RX_CHL_32 (0x3 << 8)
687 #define RT5682_I2S1_RX_CHL_8 (0x4 << 8)
715 #define RT5682_I2S_BP_MASK (0x1 << 8)
716 #define RT5682_I2S_BP_SFT 8
717 #define RT5682_I2S_BP_NOR (0x0 << 8)
718 #define RT5682_I2S_BP_INV (0x1 << 8)
737 #define RT5682_ADC_OSR_MASK (0xf << 12)
738 #define RT5682_ADC_OSR_SFT 12
739 #define RT5682_ADC_OSR_D_1 (0x0 << 12)
740 #define RT5682_ADC_OSR_D_2 (0x1 << 12)
741 #define RT5682_ADC_OSR_D_4 (0x2 << 12)
742 #define RT5682_ADC_OSR_D_6 (0x3 << 12)
743 #define RT5682_ADC_OSR_D_8 (0x4 << 12)
744 #define RT5682_ADC_OSR_D_12 (0x5 << 12)
745 #define RT5682_ADC_OSR_D_16 (0x6 << 12)
746 #define RT5682_ADC_OSR_D_24 (0x7 << 12)
747 #define RT5682_ADC_OSR_D_32 (0x8 << 12)
748 #define RT5682_ADC_OSR_D_48 (0x9 << 12)
749 #define RT5682_I2S_M_DIV_MASK (0xf << 8)
750 #define RT5682_I2S_M_DIV_SFT 8
751 #define RT5682_I2S_M_D_1 (0x0 << 8)
752 #define RT5682_I2S_M_D_2 (0x1 << 8)
753 #define RT5682_I2S_M_D_3 (0x2 << 8)
754 #define RT5682_I2S_M_D_4 (0x3 << 8)
755 #define RT5682_I2S_M_D_6 (0x4 << 8)
756 #define RT5682_I2S_M_D_8 (0x5 << 8)
757 #define RT5682_I2S_M_D_12 (0x6 << 8)
758 #define RT5682_I2S_M_D_16 (0x7 << 8)
759 #define RT5682_I2S_M_D_24 (0x8 << 8)
760 #define RT5682_I2S_M_D_32 (0x9 << 8)
761 #define RT5682_I2S_M_D_48 (0x10 << 8)
790 #define RT5682_TDM_TX_CH_MASK (0x3 << 12)
791 #define RT5682_TDM_TX_CH_2 (0x0 << 12)
792 #define RT5682_TDM_TX_CH_4 (0x1 << 12)
793 #define RT5682_TDM_TX_CH_6 (0x2 << 12)
794 #define RT5682_TDM_TX_CH_8 (0x3 << 12)
795 #define RT5682_TDM_RX_CH_MASK (0x3 << 8)
796 #define RT5682_TDM_RX_CH_2 (0x0 << 8)
797 #define RT5682_TDM_RX_CH_4 (0x1 << 8)
798 #define RT5682_TDM_RX_CH_6 (0x2 << 8)
799 #define RT5682_TDM_RX_CH_8 (0x3 << 8)
806 #define RT5682_IF1_ADC2_SEL_SFT 12
808 #define RT5682_IF1_ADC4_SEL_SFT 8
869 #define RT5682_PLL1_SRC_MASK (0x3 << 8)
870 #define RT5682_PLL1_SRC_SFT 8
871 #define RT5682_PLL1_SRC_MCLK (0x0 << 8)
872 #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8)
873 #define RT5682_PLL1_SRC_SDW (0x2 << 8)
874 #define RT5682_PLL1_SRC_RC (0x3 << 8)
890 #define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12)
891 #define RT5682_PLL_M_SFT 12
901 #define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12)
902 #define RT5682_DAC_STO1_ASRC_SFT 12
903 #define RT5682_AD_ASRC_MASK (0x1 << 8)
904 #define RT5682_AD_ASRC_SFT 8
915 #define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12)
916 #define RT5682_FILTER_CLK_SEL_SFT 12
917 #define RT5682_FILTER_CLK_DIV_MASK (0xf << 8)
918 #define RT5682_FILTER_CLK_DIV_SFT 8
923 #define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12)
924 #define RT5682_ASRCIN_FTK_N2_SFT 12
925 #define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8)
926 #define RT5682_ASRCIN_FTK_M1_SFT 8
931 #define RT5682_PLL2_OUT_MASK (0x1 << 8)
932 #define RT5682_PLL2_OUT_98M (0x0 << 8)
933 #define RT5682_PLL2_OUT_49M (0x1 << 8)
976 #define RT5682_RAMP_MASK (0x1 << 12)
977 #define RT5682_RAMP_SFT 12
978 #define RT5682_RAMP_DIS (0x0 << 12)
979 #define RT5682_RAMP_EN (0x1 << 12)
1002 #define RT5682_PM_HP_MASK (0x3 << 8)
1003 #define RT5682_PM_HP_SFT 8
1004 #define RT5682_PM_HP_LV (0x0 << 8)
1005 #define RT5682_PM_HP_MV (0x1 << 8)
1006 #define RT5682_PM_HP_HV (0x2 << 8)
1025 #define RT5682_MIC1_OVCD_MASK (0x1 << 12)
1026 #define RT5682_MIC1_OVCD_SFT 12
1027 #define RT5682_MIC1_OVCD_DIS (0x0 << 12)
1028 #define RT5682_MIC1_OVCD_EN (0x1 << 12)
1035 #define RT5682_MIC2_OV_MASK (0x3 << 8)
1036 #define RT5682_MIC2_OV_SFT 8
1037 #define RT5682_MIC2_OV_2V7 (0x0 << 8)
1038 #define RT5682_MIC2_OV_2V4 (0x1 << 8)
1039 #define RT5682_MIC2_OV_2V25 (0x3 << 8)
1040 #define RT5682_MIC2_OV_1V8 (0x4 << 8)
1061 #define RT5682_PWR_CLK1M_MASK (0x1 << 8)
1062 #define RT5682_PWR_CLK1M_SFT 8
1063 #define RT5682_PWR_CLK1M_PD (0x0 << 8)
1064 #define RT5682_PWR_CLK1M_PU (0x1 << 8)
1067 #define RT5682_PLL2F_K_MASK (0x1f << 8)
1068 #define RT5682_PLL2F_K_SFT 8
1074 #define RT5682_PLL2F_M_MASK (0x3f << 8)
1075 #define RT5682_PLL2F_M_SFT 8
1079 #define RT5682_PLL2F_N_MASK (0x7f << 8)
1080 #define RT5682_PLL2F_N_SFT 8
1085 #define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12)
1086 #define RT5682_PLL2B_PS_BYP_SFT 12
1096 #define RT5682_POW_ANA (0x1 << 12)
1152 #define RT5682_GP2_PIN_MASK (0x3 << 12)
1153 #define RT5682_GP2_PIN_SFT 12
1154 #define RT5682_GP2_PIN_GPIO2 (0x0 << 12)
1155 #define RT5682_GP2_PIN_LRCK2 (0x1 << 12)
1156 #define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12)
1162 #define RT5682_GP4_PIN_MASK (0x3 << 8)
1163 #define RT5682_GP4_PIN_SFT 8
1164 #define RT5682_GP4_PIN_GPIO4 (0x0 << 8)
1165 #define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8)
1166 #define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8)
1167 #define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8)
1188 #define RT5682_GP2_OUT_MASK (0x1 << 12)
1189 #define RT5682_GP2_OUT_L (0x0 << 12)
1190 #define RT5682_GP2_OUT_H (0x1 << 12)
1200 #define RT5682_GP4_OUT_MASK (0x1 << 8)
1201 #define RT5682_GP4_OUT_L (0x0 << 8)
1202 #define RT5682_GP4_OUT_H (0x1 << 8)
1260 /* Bias current control 8 (0x0111) */
1277 #define RT5682_CKGEN_DAC1_MASK (0x1 << 12)
1278 #define RT5682_CKGEN_DAC1_SFT 12
1283 #define RT5682_CKGEN_ADC1_MASK (0x1 << 12)
1284 #define RT5682_CKGEN_ADC1_SFT 12
1314 #define RT5682_SAR_POW_MASK (0x1 << 12)
1315 #define RT5682_SAR_POW_EN (0x1 << 12)
1316 #define RT5682_SAR_POW_DIS (0x0 << 12)
1326 #define RT5682_SAR_SEL_MB2_MASK (0x1 << 8)
1327 #define RT5682_SAR_SEL_MB2_SEL (0x1 << 8)
1328 #define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8)