Lines Matching +full:codec +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_ac97.c - Tegra20 AC97 platform driver
33 #define DRV_NAME "tegra20-ac97"
42 /* reset line is not driven by DAC pad group, have to toggle GPIO */ in tegra20_ac97_codec_reset()
43 gpio_set_value(workdata->reset_gpio, 0); in tegra20_ac97_codec_reset()
46 gpio_set_value(workdata->reset_gpio, 1); in tegra20_ac97_codec_reset()
52 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); in tegra20_ac97_codec_reset()
65 * although sync line is driven by the DAC pad group warm reset using in tegra20_ac97_codec_warm_reset()
69 gpio_request(workdata->sync_gpio, "codec-sync"); in tegra20_ac97_codec_warm_reset()
71 gpio_direction_output(workdata->sync_gpio, 1); in tegra20_ac97_codec_warm_reset()
74 gpio_set_value(workdata->sync_gpio, 0); in tegra20_ac97_codec_warm_reset()
76 gpio_free(workdata->sync_gpio); in tegra20_ac97_codec_warm_reset()
81 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); in tegra20_ac97_codec_warm_reset()
94 regmap_write(workdata->regmap, TEGRA20_AC97_CMD, in tegra20_ac97_codec_read()
102 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); in tegra20_ac97_codec_read()
118 regmap_write(workdata->regmap, TEGRA20_AC97_CMD, in tegra20_ac97_codec_write()
128 regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback); in tegra20_ac97_codec_write()
138 .reset = tegra20_ac97_codec_reset,
144 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_start_playback()
148 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL, in tegra20_ac97_start_playback()
157 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_stop_playback()
160 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL, in tegra20_ac97_stop_playback()
166 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_start_capture()
173 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR, in tegra20_ac97_stop_capture()
186 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra20_ac97_trigger()
194 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra20_ac97_trigger()
200 return -EINVAL; in tegra20_ac97_trigger()
214 dai->capture_dma_data = &ac97->capture_dma_data; in tegra20_ac97_probe()
215 dai->playback_dma_data = &ac97->playback_dma_data; in tegra20_ac97_probe()
221 .name = "tegra-ac97-pcm",
308 ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97), in tegra20_ac97_platform_probe()
311 ret = -ENOMEM; in tegra20_ac97_platform_probe()
314 dev_set_drvdata(&pdev->dev, ac97); in tegra20_ac97_platform_probe()
316 ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL); in tegra20_ac97_platform_probe()
317 if (IS_ERR(ac97->clk_ac97)) { in tegra20_ac97_platform_probe()
318 dev_err(&pdev->dev, "Can't retrieve ac97 clock\n"); in tegra20_ac97_platform_probe()
319 ret = PTR_ERR(ac97->clk_ac97); in tegra20_ac97_platform_probe()
324 regs = devm_ioremap_resource(&pdev->dev, mem); in tegra20_ac97_platform_probe()
330 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in tegra20_ac97_platform_probe()
332 if (IS_ERR(ac97->regmap)) { in tegra20_ac97_platform_probe()
333 dev_err(&pdev->dev, "regmap init failed\n"); in tegra20_ac97_platform_probe()
334 ret = PTR_ERR(ac97->regmap); in tegra20_ac97_platform_probe()
338 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node, in tegra20_ac97_platform_probe()
339 "nvidia,codec-reset-gpio", 0); in tegra20_ac97_platform_probe()
340 if (gpio_is_valid(ac97->reset_gpio)) { in tegra20_ac97_platform_probe()
341 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio, in tegra20_ac97_platform_probe()
342 GPIOF_OUT_INIT_HIGH, "codec-reset"); in tegra20_ac97_platform_probe()
344 dev_err(&pdev->dev, "could not get codec-reset GPIO\n"); in tegra20_ac97_platform_probe()
348 dev_err(&pdev->dev, "no codec-reset GPIO supplied\n"); in tegra20_ac97_platform_probe()
352 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node, in tegra20_ac97_platform_probe()
353 "nvidia,codec-sync-gpio", 0); in tegra20_ac97_platform_probe()
354 if (!gpio_is_valid(ac97->sync_gpio)) { in tegra20_ac97_platform_probe()
355 dev_err(&pdev->dev, "no codec-sync GPIO supplied\n"); in tegra20_ac97_platform_probe()
359 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1; in tegra20_ac97_platform_probe()
360 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra20_ac97_platform_probe()
361 ac97->capture_dma_data.maxburst = 4; in tegra20_ac97_platform_probe()
363 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1; in tegra20_ac97_platform_probe()
364 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in tegra20_ac97_platform_probe()
365 ac97->playback_dma_data.maxburst = 4; in tegra20_ac97_platform_probe()
367 ret = clk_prepare_enable(ac97->clk_ac97); in tegra20_ac97_platform_probe()
369 dev_err(&pdev->dev, "clk_enable failed: %d\n", ret); in tegra20_ac97_platform_probe()
375 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret); in tegra20_ac97_platform_probe()
379 ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component, in tegra20_ac97_platform_probe()
382 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); in tegra20_ac97_platform_probe()
383 ret = -ENOMEM; in tegra20_ac97_platform_probe()
387 ret = tegra_pcm_platform_register(&pdev->dev); in tegra20_ac97_platform_probe()
389 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); in tegra20_ac97_platform_probe()
393 /* XXX: crufty ASoC AC97 API - only one AC97 codec allowed */ in tegra20_ac97_platform_probe()
399 snd_soc_unregister_component(&pdev->dev); in tegra20_ac97_platform_probe()
401 clk_disable_unprepare(ac97->clk_ac97); in tegra20_ac97_platform_probe()
410 struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev); in tegra20_ac97_platform_remove()
412 tegra_pcm_platform_unregister(&pdev->dev); in tegra20_ac97_platform_remove()
413 snd_soc_unregister_component(&pdev->dev); in tegra20_ac97_platform_remove()
415 clk_disable_unprepare(ac97->clk_ac97); in tegra20_ac97_platform_remove()
423 { .compatible = "nvidia,tegra20-ac97", },