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xil-crt0.S 01/1///2/1///31//.1/1161H xil_exception.cxil_exception.hxil_types.h, .).Wf . fK].R.K-/JlK-/-K. xil_io.cxil_types.h /././.JJJJJJNfJ.J-.Nk~.J0J5Nl{ /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/lib/gcc/arm-xilinx-eabi/4.8.1/include/optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/includexil_printf.cstddef.hstdarg.hxil_printf.hstring.hctype.hd %.2,0,~f.Lp..o..p.ffHlf.c. Fnx.N2~.x.-).r.f.-/-Kg4)gN.?.3...fLHJ..(4-/z.41I/-/-h0J fu. .0 /w.2* .d0#.b.y.K4gJ-/IK-86vJB[a.dJfh.Jz.L.NJ!J2֠.:./E.1-/IK-4f ./BJ4. ./>JKf.L1L6KL10yH xtime_l.cxil_io.hxtime_l.hxil_types.h0HLiK-.Q i ../../../includexuartps.cxil_types.hxuartps.hxil_assert.hxil_io.h5} ./6.Pr.g-J/6x.-6x.61N~J4z..4./-g/of6z.,/ .Gj.!.6mN-/I30vff/1+-N].~5y..5./-g/hJ,0l5),/43)3i/`J=.q.../e/-g/KPg.JKJg fbJ5.Me.I./ .ۇ2+ .0eJ$JQ؄,0.|<6x.6./-g4.n..s.y.5z.4.g..n.//0//35/K/Qfr..l/.kS ../../../includexuartps_sinit.cxil_types.hxuartps.hmF! cpu_init.S////////1/////0gP ../../../includeoutbyte.cxil_types.hxuartps_hw.h  /W3 xil_assert.cxil_assert.h00lUO ../../../includexil_types.hxuartps.hxuartps_g.cO ../../../includexuartps_hw.cxil_types.hxil_io.hxJNK-.J2KJ3)3OmlllhllhmN*p /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/sys_exit.cunistd.h.7 getpid.c3Mo /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/syskill.cunistd.h6-/1HO-/1Ho /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/sys_sbrk.ctypes.h$5yJO0,4X. write.cxil_printf.h`=3*Kgh* JN3*Kgh* J4 close.cPH3 /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/sysfstat.c_types.htypes.hstat.hXH41+1q /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/sysisatty.cunistd.hhH6M /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/syslseek.c_types.htypes.herrno.hxH52hM2hY- read.cxil_printf.hH;3E3/I1,.N3E3/I1,. /optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/arm-xilinx-eabi/include/sys/optl/Xilinx2014.2/SDK/2014.2/gnu/arm/lin/lib/gcc/arm-xilinx-eabi/4.8.1/includeerrno.clock.h_types.hstddef.hreent.herrno.h(I8KeO ../../../includeinbyte.cxil_types.hxuartps_hw.h8I mfgpr(rn) ({unsigned int rval; __asm__ __volatile__( "mov %0,r" stringify(rn) "\n" : "=r" (rval) ); rval; })XREG_FPSCR_QC (1 << 27)XPAR_PS7_UART_1_INTR XPS_UART1_INT_IDXPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_IDXREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"__UACCUM_FBIT__ 16__APCS_32__ 1__LFRACT_EPSILON__ 0x1P-31LR__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN____UINT_LEAST32_MAX__ 4294967295ULXPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID__DBL_EPSILON__ double(2.2204460492503131e-16L)XPAR_PS7_GPIO_0_BASEADDR 0xE000A000mfcpsr() ({unsigned int rval; __asm__ __volatile__( "mrs %0, cpsr\n" : "=r" (rval) ); rval; })FALSE 0XPAR_PS7_UART_0_INTR XPS_UART0_INT_IDUSER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"__USACCUM_MIN__ 0.0UHKXPS_PMU0_INT_ID 37_REENT_L64A_BUF(ptr) ((ptr)->_new._reent._l64a_buf)XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFFXST_BUFFER_TOO_SMALL 12LXPS_FPGA8_INT_ID 84XPS_FPGA1_INT_ID 62__UACCUM_IBIT__ 16XUARTPS_TXWM_MASK 0x0000003FXREG_GPR10 r10_LONG_LONG_TYPE long longXREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50_REENT_CHECK_RAND48(ptr) XPS_DMA0_INT_ID 46UINT_LEAST8_MAX 255__FLT_MAX_10_EXP__ 38XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0XST_USB_ALREADY_CONFIGURED 1410XUARTPS_MODEMCR_RTS 0x00000002XREG_FPSCR_AHP (1 << 26)XREG_CP15_CONTROL_AFE_BIT 0x20000000XPAR_XSLCR_0_DEVICE_ID 0_VOID voidINT_LEAST16_MAX 32767XREG_CP5 5XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"__have_longlong64 1uartCfgXREG_CP15_CONTROL_TE_BIT 0x40000000XUARTPS_IXR_RXFULL 0x00000004XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFXUARTPS_IXR_DMS 0x00000200__GNUCLIKE_BUILTIN_CONSTANT_P 1XPS_SYS_CTRL_BASEADDR 0xF8000000_EXFUN(name,proto) name protoXST_TMRCTR_TIMER_FAILED 1226__printflike(fmtarg,firstvararg) __attribute__((__format__ (__printf__, fmtarg, firstvararg)))XPS_USB1_BASEADDR 0xE0003000XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"XUARTPS_MR_PARITY_ODD 0x00000008XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"XPS_DMA7_INT_ID 75XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"__ULLFRACT_IBIT__ 0XREG_GPR6 r6__SA_FBIT__ 15__DEC128_MIN_EXP__ (-6142)USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"__UDA_FBIT__ 32XIL_ASSERT_OCCURRED 1XPS_DMA2_INT_ID 48Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)XPAR_PS7_SD_0_HIGHADDR 0xE0100FFFXST_FR_TX_BUSY 1401XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"__UINT64_TYPE__ long long unsigned int__DBL_MAX_10_EXP__ 308__const constXPAR_PS7_USB_0_HIGHADDR 0xE0002FFFXPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000XST_IS_STOPPED 24L__WCHAR_TYPE__ unsigned int__GNUCLIKE___TYPEOF 1isascii(__c) ((unsigned)(__c)<=0177)__UDA_IBIT__ 32XUARTPS_MODEMSR_DSR 0x00000020__ELF__ 1XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"__SIZEOF_LONG__ 4INT_FAST16_MIN (-__STDINT_EXP(INT_MAX)-1)XST_DEVICE_IS_STARTED 5LXPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F0020014XUartPs_ConfigXPAR_XUSBPS_0_HIGHADDR 0xE0002FFFXUARTPS_IXR_TOVR 0x00001000XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_IDXPAR_XDMAPS_NUM_INSTANCES 2XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_IDXUartPs_ReadReg(BaseAddress,RegOffset) Xil_In32((BaseAddress) + (RegOffset))__WCHAR_T__ XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"XST_DEVICE_BLOCK_NOT_FOUND 3L__need___va_listXPS_QSPI_INT_ID 51__UINT_LEAST64_TYPE__ long long unsigned int_Alignas(x) __aligned(x)XPS_FIQ_INT_ID 28__P(protos) protos__INTPTR_TYPE__ intXPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID__DQ_FBIT__ 63__DBL_HAS_INFINITY__ 1___int_least32_t_defined 1XST_IIC_SELFTEST_FAILED 1076__USFRACT_MAX__ 0XFFP-8UHRXPAR_CPU_ID 0__FLT_HAS_INFINITY__ 1XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"__INT_LEAST16_MAX__ 32767__INT_MAX__ 2147483647clz(arg) ({unsigned char rval; __asm__ __volatile__( "clz %0,%1" : "=r" (rval) : "r" (arg) ); rval; })__DEC64_MIN_EXP__ (-382)XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_IDXPAR_XIICPS_1_INTR XPS_I2C1_INT_IDtostring(s) #sXUARTPS_IXR_TNFUL 0x00000800XPAR_XWDTPS_0_INTR XPS_WDT_INT_IDXREG_GPR4 r4XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"XUARTPS_OPER_MODE_LOCAL_LOOP 0x02XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000__predict_true(exp) __builtin_expect((exp), 1)XPAR_XQSPIPS_0_BASEADDR 0xE000D000XIL_EXCEPTION_ID_DATA_ABORT_INT 4XST_NOT_ENABLED 29LXPAR_PS7_I2C_0_INTR XPS_I2C0_INT_IDXUARTPS_BAUDGEN_DISABLE 0x00000000XUARTPS_SR_RXOVR 0x00000001XPS_TTC0_1_INT_ID 43__aligned(x) __attribute__((__aligned__(x)))__lock_acquire(lock) (_CAST_VOID 0)XST_SPI_COMMAND_ERROR 1162XUARTPS_MR_CHMODE_R_LOOP 0x00000300XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000_T_PTRDIFF_ XPS_AFI1_BASEADDR 0xF8009000XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)__unbounded XST_OPBARB_INVALID_PRIORITY 1176__USFRACT_MIN__ 0.0UHR_WANT_REGISTER_FINI 1XPAR_PS7_DMA_NS_DEVICE_ID 0__GNUCLIKE_BUILTIN_VAALIST 1XUARTPS_MR_STOPMODE_SHIFT 6XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000_MB_LEN_MAX 1XUARTPS_SR_RACTIVE 0x00000400XPAR_XCANPS_0_INTR XPS_CAN0_INT_IDXIL_EXCEPTION_ID_FIQ_INT 6XPAR_XTTCPS_2_BASEADDR 0xF8001008_VA_LIST_DEFINED __DEC128_MANT_DIG__ 34XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID__wchar_t__ __ARM_NEON_FP 6XREG_CPSR_FIQ_ENABLE 0x40XREG_CP15_CONTROL_NMFI_BIT 0x08000000XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZXREG_CP15_CONTROL_M_BIT 0x00000001_REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_new._reent._wcsrtombs_state)strncmpi strncasecmpXUARTPS_MR_STOPMODE_MASK 0x000000A0__fastcall __attribute__((__fastcall__))XPS_FPGA6_INT_ID 67XPAR_PS7_SD_0_BASEADDR 0xE0100000XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_IDXPS_DMAC0_SEC_BASEADDR 0xF8003000_NOINLINE __attribute__ ((__noinline__))_XPARAMETERS_PS_H_ DeviceId__LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK)XUARTPS_EVENT_RECV_ERROR 4__GCC_ATOMIC_CHAR_LOCK_FREE 2__UINT_FAST16_TYPE__ unsigned intXREG_CP15_CONTROL_TRE_BIT 0x10000000XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFFXREG_MVFR0_SP_BIT (4)XST_IIC_DTR_READBACK_ERROR 1084XPAR_XSPIPS_0_INTR XPS_SPI0_INT_IDXPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFFXREG_GPR2 r2XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000__SIZEOF_INT__ 4__ARMEL__ 1XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_IDXPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000__Static_assert(x,y) ___Static_assert(x, y)__SIG_ATOMIC_TYPE__ intXUartPs_Handler__GNUCLIKE_CTOR_SECTION_HANDLING 1XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8XPAR_PS7_XADC_0_HIGHADDR 0xF8007120XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"XPAR_PS7_TTC_0_BASEADDR 0XF8001000XPAR_PS7_DEV_CFG_0_DEVICE_ID 0XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"__UINT_LEAST64_MAX__ 18446744073709551615ULLXPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF__UINT16_C(c) c__PRAGMA_REDEFINE_EXTNAME 1XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"target_addressXREG_FPSCR c1_DEFUN_VOID(name) name(_NOARGS)XUARTPS_SR_DMS 0x00000200INST_SYNC isb()XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000XST_SPI_MODE_FAULT 1151__sym_compat(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@" #verid)XREG_FPSID_VARIANT_BIT (4)XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"___int_wchar_t_h __SYS_LOCK_H__ XREG_CP6 6XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"_REENT_CHECK_ASCTIME_BUF(ptr) __QQ_FBIT__ 7Xil_Ntohs(Data) Xil_EndianSwap16(Data)__DEC128_EPSILON__ 1E-33DLXPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687XPS_SCU_PERIPH_BASE 0xF8F00000INTPTR_MAX PTRDIFF_MAXXREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"__va_list__ 7XUartPs__BIGGEST_ALIGNMENT__ 8__UINT8_TYPE__ unsigned charUINT_FAST16_MAX (__STDINT_EXP(INT_MAX)*2U+1U)__UINT_FAST16_MAX__ 4294967295UXPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF_REENT_MBLEN_STATE(ptr) ((ptr)->_new._reent._mblen_state)XST_DMA_SG_COUNT_EXCEEDED 521LXREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"__ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLKINT_FAST32_MAX __STDINT_EXP(INT_MAX)IndexXST_SUCCESS 0L__LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;XUARTPS_IXR_RXEMPTY 0x00000002XREG_GPR0 r0XPAR_SCUGIC_0_DEVICE_ID 0XPS_AFI2_BASEADDR 0xF800A000XST_INTC_FAIL_SELFTEST 1201XPAR_PS7_SCUGIC_0_DEVICE_ID 0__FLT_DENORM_MIN__ 1.4012984643248171e-45FXPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID__SACCUM_IBIT__ 8_ANSIDECL_H_ __UINT16_TYPE__ short unsigned intXPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000XPS_IOU_S_SWITCH_BASEADDR 0xE0000000__UINT_LEAST8_MAX__ 255__EXPldr(adr) ({unsigned long rval; __asm__ __volatile__( "ldr %0,[%1]" : "=r" (rval) : "r" (adr) ); rval; })_T_SIZE_ XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF__ISO_C_VISIBLE 2011XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"__INTPTR_MAX__ 2147483647XUARTPS_MR_OFFSET 0x04INT_LEAST32_MAX 2147483647LXPS_SPI0_BASEADDR 0xE0006000_ATEXIT_SIZE 32XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040XST_SPI_NOT_MASTER 1157XST_EMAC_COLLISION_ERROR 1007LXPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFFXUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK__INT8_C(c) cXPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100__ARM_EABI__ 1__inline inline__printf0like(fmtarg,firstvararg) XPS_FPGA_AXI_S0_BASEADDR 0x40000000XUARTPS_IXR_TOUT 0x00000100XPAR_PL_RAM_0_S_AXI_HIGHADDR 0x5FFFFFFFXREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"__IEEE_LITTLE_ENDIAN __FLT_MAX_EXP__ 128__DBL_MIN__ double(2.2250738585072014e-308L)__ATOMIC_SEQ_CST 5stricmp strcasecmp_GCC_SIZE_T XPS_CAN0_INT_ID 60_X 0100_REENT_CHECK_SIGNAL_BUF(ptr) _L 02XUARTPS_MR_PARITY_NONE 0x00000020__DBL_MAX__ double(1.7976931348623157e+308L)XST_MEMTEST_FAILED 401LXPS_FPGA13_INT_ID 89__CC_SUPPORTS_WARNING 1XIL_EXCEPTION_ID_SWI_INT 2Xil_AssertVoidAlways() { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return; }__UINT_FAST8_TYPE__ unsigned intXIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INTXREG_FPSID_IMPLEMENTER_BIT (24)XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"__UTA_FBIT__ 64__DBL_DIG__ 15XREG_MVFR0_RMODE_BIT (28)__EXP(x) __ ##x ##____DECIMAL_DIG__ 17XUARTPS_MR_PARITY_SHIFT 3_NEWLIB_VERSION "2.0.0"__long_double_t long doubleXPAR_PS7_UART_1_HAS_MODEM 0XPAR_PS7_USB_0_INTR XPS_USB0_INT_IDXPS_CAN1_BASEADDR 0xE0009000__has_feature(x) 0XPAR_XDCFG_NUM_INSTANCES 1_REENT_EMERGENCY_SIZE 25__UTA_IBIT__ 64__RAND_MAX 0x7fffffffdmb() __asm__ __volatile__ ("dmb" : : : "memory")XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)XPS_WDT_BASEADDR 0xF8005000XUARTPS_IXR_OVER 0x00000020XST_FLASH_ERROR 1128L_CONST constXPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50__LFRACT_IBIT__ 0ldrb(adr) ({unsigned char rval; __asm__ __volatile__( "ldrb %0,[%1]" : "=r" (rval) : "r" (adr) ); rval; })__USER_LABEL_PREFIX__ __attribute_malloc__ _SIZE_T_DECLARED XST_FIFO_ERROR 7LXPAR_PS7_DMA_NS_BASEADDR 0xF8004000XUARTPS_IXR_MASK 0x00001FFFXST_PLBARB_FAIL_SELFTEST 1276LXPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000_HAVE_STDC __QQ_IBIT__ 0UINT16_MAX 65535XPAR_PS7_XADC_0_BASEADDR 0xF8007100__ARM_FEATURE_SIMD32 1XPS_TTC0_0_INT_ID 42XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"XREG_CR9 cr9__GNUC_PATCHLEVEL__ 1__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1XPS_GEM1_BASEADDR 0xE000C000XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLEXUARTPS_MR_CHMODE_NORM 0x00000000XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)strcmpi strcasecmp__nonnull(x) __attribute__((__nonnull__(x)))XUARTPS_RXWM_OFFSET 0x20__LDBL_MAX__ 1.7976931348623157e+308LXUARTPS_CR_TXRST 0x00000002XPS_USB1_INT_ID 76XST_PFIFO_LACK_OF_DATA 501L__LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK__LLFRACT_MIN__ (-0.5LLR-0.5LLR)XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1__LDBL_MIN_EXP__ (-1021)__DBL_MIN_10_EXP__ (-307)XST_IIC_TBA_REG_RESET_ERROR 1082__UFRACT_MIN__ 0.0URSLEEP_H _GCC_PTRDIFF_T XPS_SCU_TMR_INT_ID 29__cplusplus 199711L__FLT_MIN_10_EXP__ (-37)__UINT32_MAX__ 4294967295ULXST_PFIFO_BAD_REG_VALUE 503Lisb() __asm__ __volatile__ ("isb" : : : "memory")XREG_MVFR1 c6XREG_CP15_CONTROL_HA_BIT 0x00020000Xil_Ntohl(Data) Xil_EndianSwap32(Data)__UDQ_IBIT__ 0XUARTPS_CR_TORST 0x00000040__DBL_MANT_DIG__ 53__SACCUM_MIN__ (-0X1P7HK-0X1P7HK)XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF__FBSDID(s) struct __hackXPS_FPGA5_INT_ID 66__ULLACCUM_MIN__ 0.0ULLK__INT_WCHAR_T_H Xil_In16LE(Addr) Xil_In16(Addr)XST_IIC_ADR_READBACK_ERROR 1086XREG_CP7 7__DEC32_EPSILON__ 1E-6DFXUARTPS_MODEMCR_OFFSET 0x24XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)_WCHAR_T_DEFINED __INT_FAST8_MAX__ 2147483647XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID__size_t XUartPs_EnableUart(InstancePtr) Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), ((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN)))XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"XPAR_DDR_MEM_BASEADDR 0x00000000UINT8_C(x) xXil_AssertNonvoid(Expression) { if (Expression) { Xil_AssertStatus = XIL_ASSERT_NONE; } else { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return 0; } }XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"XREG_FPSID_SOFTWARE (1<<23)XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1__UINT32_TYPE__ long unsigned intXST_INVALID_PARAM 15L__FLT_EPSILON__ 1.1920928955078125e-7F__GNUCLIKE___OFFSETOF 1__USA_IBIT__ 16XST_DMA_BD_ERROR 527L__UINT8_C(c) cXST_DMA_SG_IS_STARTED 514L__CC_SUPPORTS_INLINE 1XPAR_PS7_QSPI_0_QSPI_MODE 0XST_DMA_SG_NOTHING_TO_COMMIT 519LTRUE 1XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"XST_PLB2OPB_FAIL_SELFTEST 1301L__ULFRACT_MAX__ 0XFFFFFFFFP-32ULRXPS_WDT_INT_ID 41XST_DMA_SG_IS_STOPPED 515L__flexarr [0]__GNUG__ 4_REENT_RAND48_ADD(ptr) ((ptr)->_new._reent._r48._add)XPAR_XDCFG_0_BASEADDR 0xF8007000__ULLFRACT_MIN__ 0.0ULLRXPS_IRQ_INT_ID 31XREG_FPSID c0XST_UART_START_ERROR 1052LXUARTPS_TXWM_OFFSET 0x44_RAND48_SEED_0 (0x330e)XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"__LONG_LONG_MAX__ 9223372036854775807LL_SYS_REENT_H_ _VOLATILE volatilecpsidi() __asm__ __volatile__("cpsid i\n")__ORDER_LITTLE_ENDIAN__ 1234_REENT_SIGNGAM(ptr) ((ptr)->_new._reent._gamma_signgam)XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFFXPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000__strong_reference(sym,aliassym) extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))XST_SPI_TRANSMIT_UNDERRUN 1153XPS_DMA3_INT_ID 49__FLT_DIG__ 6__INT_LEAST64_MAX__ 9223372036854775807LLXREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"XUARTPS_MAX_RATE 921600__DBL_MAX_EXP__ 1024XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"XPAR_XUSBPS_NUM_INSTANCES 1unsigned signedXREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"XUARTPS_IDR_OFFSET 0x0CSIG_ATOMIC_MAX __STDINT_EXP(INT_MAX)XST_EMAC_PARSE_ERROR 1006L_REENT_STRTOK_LAST(ptr) ((ptr)->_new._reent._strtok_last)__EXCEPTIONS 1__GNUCLIKE___SECTION 1XUINT64_LSW(x) ((x).Lower)__SIZEOF_SIZE_T__ 4XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"__DEC128_MAX__ 9.999999999999999999999999999999999E6144DLXREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"__INT_FAST16_TYPE__ intXUartPs_WriteReg(BaseAddress,RegOffset,RegisterValue) Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))__LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLRXPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061FXREG_CP15_CONTROL_Z_BIT 0x00000800XUartPs_IsReceiveData(BaseAddress) !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY)INT_FAST16_MAX __STDINT_EXP(INT_MAX)HAVE_INITFINI_ARRAY 1XUARTPS_MR_CHARLEN_MASK 0x00000006XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"XREG_GPR14 r14__format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg)))XUARTPS_RXWM_RESET_VAL 0x00000020XPS_DMA4_INT_ID 72__WINT_MAX__ 4294967295UXPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDRXPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID__UACCUM_EPSILON__ 0x1P-16UKXST_NAND_OPT_NOT_SUPPORTED 1445LXREG_FPEXC_EX (1 << 31)__SFRACT_FBIT__ 7__LLACCUM_EPSILON__ 0x1P-31LLKXST_NOT_SGDMA 16LPTRDIFF_MIN (-PTRDIFF_MAX - 1)XUARTPS_SR_TTRIG 0x00002000__DBL_DECIMAL_DIG__ 17__SIZEOF_LONG_LONG__ 8XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)__INT_LEAST64_TYPE__ long long intXPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_IDWCHAR_MAX __WCHAR_MAX__XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"__SIG_ATOMIC_MAX__ 2147483647__ARM_ARCH_PROFILE 65XST_NAND_PART_NOT_SUPPORTED 1444L_WCHAR_T_DEFINED_ XUARTPS_RXTOUT_MASK 0x000000FF__CS_SOURCERYGXX_MIN__ 11__bounded __WINT_TYPE__ unsigned intXREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"XUARTPS_SR_PARITY 0x00000080__SIZE_MAX__ 4294967295U_ATEXIT_DYNAMIC_ALLOC 1XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000XREG_FPSCR_N_BIT (1 << 31)XUartPs_IsTransmitFull(BaseAddress) ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL)__FLT_MANT_DIG__ 24XST_SPI_TRANSFER_DONE 1152XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8__ULACCUM_FBIT__ 32XST_SEND_ERROR 28L__va_copy(d,s) __builtin_va_copy(d,s)XUARTPS_ISR_OFFSET 0x14__GNUC_VA_LIST_COMPATIBILITY 1NULL __null__ARM_FP 14XREG_FPSCR_C_BIT (1 << 29)XUARTPS_HW_H XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_IDXPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR___int16_t_defined 1XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"__GNUCLIKE_MATH_BUILTIN_RELOPS XUARTPS_MIN_RATE 110XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"INT_LEAST64_MIN (-9223372036854775807LL-1LL)__ARM_NEON 1XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"__XSI_VISIBLE 700XPS_TOP_BUS_CFG_BASEADDR 0xF8900000XPS_CORE_PARITY0_INT_ID 32__DEC32_MIN__ 1E-95DF__UQQ_FBIT__ 8__FLT_MIN_EXP__ (-125)XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI__UINT_FAST64_MAX__ 18446744073709551615ULLXUARTPS_MR_PARITY_SPACE 0x00000010__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN___EXFUN_NOTHROW(name,proto) name proto _NOTHROW__UINT64_C(c) c ## ULL__FRACT_IBIT__ 0XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687__FLT_RADIX__ 2__USA_FBIT__ 16_ANSI_STDARG_H_ XST_IPIF_IP_STATUS_ERROR 536L_BEGIN_STD_C extern "C" {XPS_SPI0_INT_ID 58XREG_CP8 8__LDBL_EPSILON__ 2.2204460492503131e-16LXPS_PARPORT0_BASEADDR 0xE2000000XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID__SQ_FBIT__ 31INT64_MIN (-9223372036854775807LL-1LL)IsReadyXREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)__ACCUM_EPSILON__ 0x1P-15K_VA_LIST_ ModemPinsConnected__DEC128_MAX_EXP__ 6145__LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LKXPAR_PS7_USB_0_BASEADDR 0xE0002000XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_IDXREG_GPR3 r3XPAR_XQSPIPS_0_QSPI_MODE 0__FLT_EVAL_METHOD__ 0XPAR_XSDPS_0_BASEADDR 0xE0100000__VERSION__ "4.8.1"XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"__DEC32_SUBNORMAL_MIN__ 0.000001E-95DF__INT64_MAX__ 9223372036854775807LL_Z12test_addressmXREG_GPR11 r11XST_NAND_ERROR 1443L__FRACT_EPSILON__ 0x1P-15RXREG_CORTEXA9_H __lock_release(lock) (_CAST_VOID 0)XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_IDXPS_FPGA3_INT_ID 64XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000XUARTPS_IXR_FRAMING 0x00000040XREG_CPSR_N_BIT 0x80000000XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"XPAR_PL_RAM_0_DEVICE_ID 0XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_IDXPAR_XUARTPS_0_HIGHADDR 0xE0001FFF__UDQ_FBIT__ 64XUARTPS_IER_OFFSET 0x08__int_fast8_t_defined 1XPS_TTC0_BASEADDR 0xF8001000XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF__SFRACT_IBIT__ 0__weak_reference(sym,alias) __asm__(".weak " #alias); __asm__(".equ " #alias ", " #sym)XPS_DMA6_INT_ID 74XUARTPS_EVENT_SENT_DATA 3___int64_t_defined 1__need_NULL __GNUCLIKE_BUILTIN_NEXT_ARG 1_toupper(__c) ((unsigned char)(__c) - 'a' + 'A')XREG_CPSR_IRQ_MODE 0x12XST_FLASH_ADDRESS_ERROR 1135LXPS_FPGA9_INT_ID 85XPS_USB0_BASEADDR 0xE0002000__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2va_arg(v,l) __builtin_va_arg(v,l)__INT16_TYPE__ short intXST_OPB2PLB_FAIL_SELFTEST 1326L_C 040__int_fast16_t_defined 1_REENT_RAND48_SEED(ptr) ((ptr)->_new._reent._r48._seed)XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"__FRACT_MIN__ (-0.5R-0.5R)__ULFRACT_FBIT__ 32__GNUCLIKE_BUILTIN_MEMCPY 1___int_size_t_h __sym_default(sym,impl,verid) __asm__(".symver " #impl ", " #sym "@@" #verid)_Static_assert(x,y) __Static_assert(x, __COUNTER__)XST_EMAC_MEMORY_SIZE_ERROR 1001LXUARTPS_IXR_RXOVR 0x00000001__GCC_ATOMIC_LONG_LOCK_FREE 2XST_NAND_READY 1442L__int_fast32_t_defined 1PTRDIFF_MAX __PTRDIFF_MAX____GXX_TYPEINFO_EQUALITY_INLINE 0XPAR_XEMACPS_NUM_INSTANCES 1__UHQ_FBIT__ 16__WINT_MIN__ 0UXPS_SDIO1_INT_ID 79__GNUC_MINOR__ 8__lock_init(lock) (_CAST_VOID 0)userInputXUARTPS_MODEMSR_TERI 0x00000004XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"__compiler_membar() __asm __volatile(" " : : : "memory")print_main_menuXUARTPS_OPTION_RESET_RX 0x0008XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"XREG_FPSID_REV_BIT (0)XST_DMA_SG_LIST_EMPTY 513LXREG_CPSR_SYSTEM_MODE 0x1FXST_FLASH_TOO_MANY_REGIONS 1133LXUARTPS_MODEMSR_DDCD 0x00000008XUARTPS_H __WCHAR_MIN__ 0U_REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_new._reent._mbsrtowcs_state)XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_IDXUARTPS_CR_TX_DIS 0x00000020_REENT_CHECK_MP(ptr) XPAR_XDCFG_0_INTR XPS_DVC_INT_ID__INT_LEAST32_MAX__ 2147483647L__CC_SUPPORTS___INLINE 1_GCC_WCHAR_T XUARTPS_FORMAT_1_STOP_BIT 0__LOCK_INIT(class,lock) static int lock = 0;XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"XREG_FPSCR_IDC (1 << 7)XPAR_PS7_TTC_1_DEVICE_ID 1XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZXREG_MVFR0_SHORT_VEC_BIT (24)__LLFRACT_EPSILON__ 0x1P-63LLRXUARTPS_SR_RXFULL 0x00000004XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620__FRACT_FBIT__ 15mtgpr(rn,v) __asm__ __volatile__( "mov r" stringify(rn) ", %0 \n" : : "r" (v) )__dead2 __attribute__((__noreturn__))XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)__need_size_t va_start(v,l) __builtin_va_start(v,l)__ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULKXREG_CP14 14dsb() __asm__ __volatile__ ("dsb" : : : "memory")__volatile volatile__CHAR_UNSIGNED__ 1XUARTPS_OPTION_RESET_TX 0x0010_BSD_WCHAR_T_XUARTPS_EVENT_MODEM 5XUARTPS_MR_CHARLEN_7_BIT 0x00000004__GCC_HAVE_DWARF2_CFI_ASM 1XREG_CPSR_THUMB_MODE 0x20XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"XREG_FPSCR_OFC (1 << 2)__UINTMAX_MAX__ 18446744073709551615ULLXREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"__need_size_tXST_ATMC_ERROR_COUNT_MAX 1101LXPAR_XCANPS_1_INTR XPS_CAN1_INT_ID__ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLRXPS_AFI0_BASEADDR 0xF8008000XST_OPBARB_NOT_SUSPENDED 1177XST_UART_BAUD_ERROR 1055L__DQ_IBIT__ 0XST_UART_INIT_ERROR 1051L__HA_FBIT__ 7__UACCUM_MIN__ 0.0UKXREG_CP15_CONTROL_RR_BIT 0x00004000toascii(__c) ((__c)&0177)__DEC128_MIN__ 1E-6143DL__GNUCLIKE_ASM 3XST_IIC_BUS_BUSY 1077__lock_close(lock) (_CAST_VOID 0)__UFRACT_EPSILON__ 0x1P-16UR__DEC64_MANT_DIG__ 16XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID__FLT_HAS_QUIET_NAN__ 1XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_IDSTDOUT_BASEADDRESS 0xE0001000_GCC_WRAP_STDINT_H XPS_SPI1_BASEADDR 0xE0007000__WCHAR_UNSIGNED__ 1XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x0100)XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"__INT_FAST64_MAX__ 9223372036854775807LLXPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZXPS_FPGA10_INT_ID 86XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_IDXPAR_PS7_QSPI_0_DEVICE_ID 0XST_UART_BAUD_RANGE 1056LXUARTPS_OPTION_ASSERT_RTS 0x0004XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF_REENT_MP_RESULT_K(ptr) ((ptr)->_result_k)XUINT64_MSW(x) ((x).Upper)XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ__LONG_MAX__ 2147483647LXPS_I2C0_BASEADDR 0xE0004000__ORDER_PDP_ENDIAN__ 3412XREG_CR10 cr10XREG_CPSR_DATA_ABORT_MODE 0x17strnicmp strncasecmpXPAR_XGPIOPS_0_INTR XPS_GPIO_INT_IDXPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1XREG_FPSCR_STRIDE_BIT (20)XREG_CP9 9__INT_FAST64_TYPE__ long long int_REENT_MBTOWC_STATE(ptr) ((ptr)->_new._reent._mbtowc_state)XREG_CP12 12__noinline __attribute__ ((__noinline__))RequestedBytesXST_SPI_SLAVE_ONLY 1158XST_FLASH_BUSY 1126L__attribute_pure__ _HAVE_LONG_DOUBLE 1__ARM_FEATURE_QBIT 1__UINT32_C(c) c ## ULXPAR_PS7_TTC_0_DEVICE_ID 0_REENT_WCTOMB_STATE(ptr) ((ptr)->_new._reent._wctomb_state)__ARM_FEATURE_UNALIGNED 1__SACCUM_MAX__ 0X7FFFP-7HK__section(x) __attribute__((__section__(x)))GNU C++ 4.8.1 -march=armv7-a -mfloat-abi=softfp -mfpu=neon-fp16 -g3 -O0 -fmessage-length=0INT_FAST64_MAX INT_LEAST64_MAXXREG_CP15_CONTROL_SW_BIT 0x00000400XST_OPBARB_PARK_NOT_ENABLED 1178XPS_L2CC_INT_ID 34__ACCUM_IBIT__ 16XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_IDXREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000__GNUC_VA_LIST XIL_PRINTF_H XPS_UART1_INT_ID 82XUARTPS_RXTOUT_DISABLE 0x00000000XUARTPS_MR_CHMODE_L_LOOP 0x00000200XUARTPS_BAUDDIV_MASK 0x000000FF_Z15print_main_menuvXREG_FPSCR_IOC (1 << 0)XUARTPS_SR_RXEMPTY 0x00000002XREG_CR12 cr12XPAR_PS7_TTC_2_DEVICE_ID 2__need_wint_tXPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000__ATOMIC_RELAXED 0__LDBL_MIN__ 2.2250738585072014e-308LXPAR_SCUGIC_SINGLE_DEVICE_ID 0__ULACCUM_IBIT__ 32XPAR_XTTCPS_1_BASEADDR 0xF8001004XPS_SDIO1_BASEADDR 0xE0101000XUARTPS_FORMAT_MARK_PARITY 3__THUMB_INTERWORK__ 1XPS_AFI3_BASEADDR 0xF800B000__has_builtin(x) 0XUARTPS_SR_TACTIVE 0x00000800__POSIX_VISIBLE 200809__FRACT_MAX__ 0X7FFFP-15R_DEFUN(name,arglist,args) name(args)__returns_twice __attribute__((__returns_twice__))XPS_NAND_BASEADDR 0xE1000000XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"_REENT_MP_RESULT(ptr) ((ptr)->_result)XST_NAND_CACHE_ERROR 1450LXPS_SDIO0_INT_ID 56__LLFRACT_IBIT__ 0XST_DMA_SG_BD_LOCKED 518LXST_IIC_TX_FIFO_REG_RESET_ERROR 1080XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)__UFRACT_IBIT__ 0XST_INTC_CONNECT_ERROR 1202XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000XST_NO_DATA 13LXPAR_SCUWDT_INTR XPS_SCU_WDT_INT_IDXREG_CP10 10_REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))__SFRACT_MAX__ 0X7FP-7HRXREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"__ptrvalue XPS_PMU1_INT_ID 38XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115_NULL 0XPS_FPGA2_INT_ID 63XST_PFIFO_ERROR 504LXREG_CPSR_Z_BIT 0x40000000__ARM_ARCH_ISA_ARM 1_WCHAR_T_DECLARED XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)__containerof(x,s,m) ({ const volatile __typeof__(((s *)0)->m) *__x = (x); __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));})_REENT_CHECK_EMERGENCY(ptr) _UNBUF_STREAM_OPT 1XPS_DMA1_INT_ID 47XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID__GXX_ABI_VERSION 1002XPAR_PS7_SD_0_DEVICE_ID 0_REENT_INIT_PTR(var) { memset((var), 0, sizeof(*(var))); (var)->_stdin = &(var)->__sf[0]; (var)->_stdout = &(var)->__sf[1]; (var)->_stderr = &(var)->__sf[2]; (var)->_current_locale = "C"; (var)->_new._reent._rand_next = 1; (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; (var)->_new._reent._r48._add = _RAND48_ADD; }XST_ERROR_COUNT_MAX 22LXST_DMA_TRANSFER_ERROR 511LXST_FR_TX_ERROR 1400XIL_EXCEPTION_ID_UNDEFINED_INT 1XST_IIC_CR_READBACK_ERROR 1083__CC_SUPPORTS___FUNC__ 1uart__UTQ_IBIT__ 0XPS_GPIO_BASEADDR 0xE000A000XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFFXREG_FPSCR_ROUND_TOZERO (3 << 22)__SIZEOF_WINT_T__ 4__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)XST_FLASH_NOT_SUPPORTED 1132LXUARTPS_OPER_MODE_REMOTE_LOOP 0x03XUARTPS_CR_RXRST 0x00000001XPS_I2C1_INT_ID 80__ARM_FEATURE_SAT 1XUARTPS_DFT_BAUDRATE 115200XUARTPS_SR_TOUT 0x00000100XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"XPAR_SCUGIC_ACK_BEFORE 0__FLT_MAX__ 3.4028234663852886e+38FXPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID__INT_LEAST8_TYPE__ signed char_T_WCHAR __DEVOLATILE(type,var) ((type)(uintptr_t)(volatile void *)(var))XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_IDPL_RAM_H mtcp(rn,v) __asm__ __volatile__( "mcr " rn "\n" : : "r" (v) );XREG_GPR9 r9XREG_MVFR0_DIVIDE_BIT (16)__SIZEOF_WCHAR_T__ 4XUARTPS_MR_CHARLEN_8_BIT 0x00000000XUARTPS_BAUDGEN_OFFSET 0x18__USACCUM_MAX__ 0XFFFFP-8UHKXIL_ASSERT_H INT32_MIN (-2147483647L-1)_CTYPE_H_ XREG_FPSCR_Z_BIT (1 << 30)XUARTPS_IXR_PARITY 0x00000080XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0__lock_try_acquire(lock) (_CAST_VOID 0)__ATOMIC_ACQUIRE 2XPAR_XIICPS_0_INTR XPS_I2C0_INT_IDXREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID__GNUCLIKE_BUILTIN_VARARGS 1_Kmax (sizeof (size_t) << 3)__ASMNAME(cname) __XSTRING (__USER_LABEL_PREFIX__) cname_Thread_local __threadXPAR_XDCFG_0_HIGHADDR 0xF80070FFXPS_CAN0_BASEADDR 0xE0008000__USACCUM_EPSILON__ 0x1P-8UHK___int_least16_t_defined 1XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ__has_include(x) 0XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000XPAR_XDMAPS_1_BASEADDR 0xF8003000XUARTPS_IXR_TXFULL 0x00000010__INTMAX_C(c) c ## LL__LACCUM_MIN__ (-0X1P31LK-0X1P31LK)XUARTPS_RXWM_MASK 0x0000003F__UINT_FAST64_TYPE__ long long unsigned intXREG_CPSR_SVC_MODE 0x13_REENT_RAND_NEXT(ptr) ((ptr)->_new._reent._rand_next)XST_FLASH_ERASE_SUSPENDED 1129LXUARTPS_MR_CLKSEL 0x00000001XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFUINT_FAST64_MAX UINT_LEAST64_MAXXREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"XREG_FPSID_ARCH_BIT (16)__used __attribute__((__used__))XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_IDXST_RESET_ERROR 8L_RAND48_MULT_0 (0xe66d)XPAR_PS7_TTC_1_BASEADDR 0XF8001004XPAR_XUARTPS_0_BASEADDR 0xE0001000XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"XREG_FPEXC_DEX (1 << 29)XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600_REENT_EMERGENCY(ptr) ((ptr)->_emergency)XST_DMA_SG_NO_LIST 523L_U 01XREG_CPSR_V_BIT 0x10000000XST_IPIF_IP_ACK_ERROR 537LXST_USB_NO_DESC_AVAILABLE 1412XPS_UART1_BASEADDR 0xE0001000_REENT _impure_ptrXPS_OCMINTR_INT_ID 35XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"XPAR_PS7_GPIO_0_DEVICE_ID 0__SQ_IBIT__ 0XUARTPS_MODEMCR_FCM 0x00000010XUARTPS_FORMAT_ODD_PARITY 1XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"__need_NULLXPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8XUARTPS_MR_STOPMODE_2_BIT 0x00000080XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZXST_FLASH_READY 1127L__always_inline __attribute__((__always_inline__))XST_IPIF_REG_WIDTH_ERROR 531LXPAR_PS7_SPI_1_INTR XPS_SPI1_INT_IDXPS_QSPI_LINEAR_BASEADDR 0xFC000000XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"XST_IPIF_DEVICE_ID_ERROR 540LXST_SPI_NO_SLAVE 1155XREG_GPR7 r7__packed __attribute__((__packed__))XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_IDXPAR_XTTCPS_0_TTC_CLK_CLKSRC 0__SFRACT_MIN__ (-0.5HR-0.5HR)Xil_Out16LE(Addr,Value) Xil_Out16(Addr, Value)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1__LACCUM_FBIT__ 31XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"XUARTPS_OPTION_RESET_TMOUT 0x0020__ULACCUM_MIN__ 0.0ULKXPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZINT_LEAST32_MIN (-2147483647L-1)XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_IDXUARTPS_MR_PARITY_MASK 0x00000038_SYS__TYPES_H _RAND48_SEED_2 (0x1234)XREG_CP15_CONTROL_EE_BIT 0x02000000XST_SPI_RECEIVE_NOT_EMPTY 1161__RCSID(s) struct __hack__INT32_C(c) c ## L_AND ,XREG_FPEXC_EN (1 << 30)__USQ_IBIT__ 0sizetypeXPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID__DEC64_EPSILON__ 1E-15DDXPAR_XEMACPS_0_INTR XPS_GEM0_INT_IDXREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"__GNUCLIKE_BUILTIN_STDARG 1__int_least8_t_defined 1__DEC32_MAX_EXP__ 97XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_IDXST_IPIF_DEVICE_ACK_ERROR 534LXPS_FPGA_AXI_S1_BASEADDR 0x80000000__SACCUM_EPSILON__ 0x1P-7HKXUARTPS_SR_OFFSET 0x2CXST_VDMA_MISMATCH_ERROR 1430XPS_FPGA7_INT_ID 68XREG_FPINST c9XIL_TYPES_H XREG_CP0 0InputClockHzXST_IIC_TBA_READBACK_ERROR 1087__lock_acquire_recursive(lock) (_CAST_VOID 0)XST_DMA_SG_BD_NOT_COMMITTED 524L__lock_release_recursive(lock) (_CAST_VOID 0)XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"__size_t__ __SYS_CONFIG_H__ _REENT_INIT(var) { 0, &(var).__sf[0], &(var).__sf[1], &(var).__sf[2], 0, "", 0, "C", 0, _NULL, _NULL, 0, _NULL, _NULL, 0, _NULL, { { 0, _NULL, "", {0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 1, { {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, _RAND48_ADD }, {0, {0}}, {0, {0}}, {0, {0}}, "", "", 0, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}}, {0, {0}} } }, _REENT_INIT_ATEXIT _NULL, {_NULL, 0, _NULL} }XUARTPS_TXWM_RESET_VAL 0x00000020__predict_false(exp) __builtin_expect((exp), 0)XPS_EFUSE_BASEADDR 0xF800D000XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC_PTR void *WINT_MAX __WINT_MAX___END_STD_C }__ULLACCUM_EPSILON__ 0x1P-32ULLK__CHAR_BIT__ 8Xil_Htons(Data) Xil_EndianSwap16(Data)__INTMAX_TYPE__ long long intXPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200)_POINTER_INT longXREG_GPR5 r5XST_NAND_ADDRESS_ERROR 1447LXPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000XPAR_PS7_SCUTIMER_0_DEVICE_ID 0XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000__INT16_MAX__ 32767XUARTPS_RXWM_DISABLE 0x00000000_GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit)UINT64_MAX 18446744073709551615ULL_BSD_SIZE_T_ UINT32_C(x) x ##ULXPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115XUARTPS_IXR_TXEMPTY 0x00000008XST_IIC_NOT_SLAVE 1088_STRING_H_ XPAR_SCUWDT_0_BASEADDR 0xF8F00620UINT_LEAST64_MAX 18446744073709551615ULLXPS_DMA0_ABORT_INT_ID 45__GXX_RTTI 1__CC_SUPPORTS_VARADIC_XXX 1__BEGIN_DECLS extern "C" {XST_FIFO_NO_ROOM 11LXPS_PERIPHERAL_BASEADDR 0xE0000000XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000_BSD_SIZE_T_DEFINED_ XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF__GCC_ATOMIC_POINTER_LOCK_FREE 2XPS_TTC1_BASEADDR 0xF8002000XPS_SCU_WDT_INT_ID 30INT_LEAST8_MIN -128_RAND48_MULT_1 (0xdeec)XREG_CR7 cr7XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"__DOTS , ...__hidden __attribute__((__visibility__("hidden")))XPS_FPGA0_INT_ID 61INTPTR_MIN PTRDIFF_MIN_REENT_RAND48_MULT(ptr) ((ptr)->_new._reent._r48._mult)XPAR_XGPIOPS_0_BASEADDR 0xE000A000__DEC64_MAX_EXP__ 385XREG_CP15_CONTROL_V_BIT 0x00002000_REENT_MBRTOWC_STATE(ptr) ((ptr)->_new._reent._mbrtowc_state)XUARTPS_EVENT_RECV_TOUT 2__ACCUM_FBIT__ 15__LDBL_HAS_DENORM__ 1_ANSI_STDDEF_H XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115XPS_PERIPH_APB_BASEADDR 0xF8000000XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"XUARTPS_MR_CHARLEN_6_BIT 0x00000006__UINT_FAST8_MAX__ 4294967295U_RAND48_MULT_2 (0x0005)XREG_FPSID_PART_BIT (8)XST_NOT_INTERRUPT 20L__USES_INITFINI__ 1__XUINT64__ __GCC_ATOMIC_INT_LOCK_FREE 2__has_extension __has_feature__REGISTER_PREFIX__ XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_IDXPAR_GLOBAL_TMR_NUM_INSTANCES 1mfcp(rn) ({unsigned int rval; __asm__ __volatile__( "mrc " rn "\n" : "=r" (rval) ); rval; })XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZXREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"XPAR_XTTCPS_NUM_INSTANCES 3Xil_AssertNonvoidAlways() { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return 0; }XST_SPI_TOO_MANY_SLAVES 1156XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"INT_FAST8_MIN (-__STDINT_EXP(INT_MAX)-1)XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFFXST_PFIFO_NO_ROOM 502LXUARTPS_BAUDDIV_RESET_VAL 0x0000000F__warn_references(sym,msg) __asm__(".section .gnu.warning." #sym); __asm__(".asciz \"" msg "\""); __asm__(".previous")_REENT_ASCTIME_BUF(ptr) ((ptr)->_new._reent._asctime_buf)Xil_In32LE(Addr) Xil_In32(Addr)XPS_GEM1_WAKE_INT_ID 78XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"__USQ_FBIT__ 32XST_USB_BUF_TOO_BIG 1413__INT_FAST8_TYPE__ intXPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)__ptr_t void *XST_USB_NO_BUF 1414XST_NAND_TIMEOUT_ERROR 1446LXPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID__INT_FAST16_MAX__ 2147483647unsigned__STDC_HOSTED__ 1__UINTMAX_C(c) c ## ULL__DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD__need_ptrdiff_tXPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFFXST_DMA_SG_LIST_ERROR 526LXPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5XUARTPS_IMR_OFFSET 0x10__UACCUM_MAX__ 0XFFFFFFFFP-16UK_WINT_T XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF__UHQ_IBIT__ 0XST_LOOPBACK_ERROR 17L_PARAMS(paramlist) paramlistXST_IPIF_DEVICE_ENABLE_ERROR 535L_SIGNED signedXPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID_REENT_MP_P5S(ptr) ((ptr)->_p5s)XPS_TTC0_2_INT_ID 44__DBL_HAS_DENORM__ 1XREG_FPSCR_UFC (1 << 3)XPS_CORESIGHT_BASEADDR 0xF8800000__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1_GLOBAL_REENT _global_impure_ptrXST_INVALID_VERSION 4LXREG_FPSCR_DZC (1 << 1)_N_LISTS 30__PTRDIFF_TYPE__ intXST_IPIF_RESET_REGISTER_ERROR 532L__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2XPAR_SCUGIC_NUM_INSTANCES 1__USACCUM_FBIT__ 8XREG_GPR1 r1XUARTPS_MODEMSR_CTS 0x00000010__LACCUM_EPSILON__ 0x1P-31LKXPS_FPGA14_INT_ID 90XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100XUartPs_SetModeControl(InstancePtr,RegisterValue) Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, (RegisterValue))XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"UINT8_MAX 255__EXPORT __PMT(args) argsINTMAX_MIN (-INTMAX_MAX - 1)XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFFXPS_GLOBAL_TMR_INT_ID 27XREG_CR4 cr4XST_PFIFO_DEADLOCK 505L__UTQ_FBIT__ 128__strftimelike(fmtarg,firstvararg) __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))RemainingBytesXUARTPS_MR_STOPMODE_1_BIT 0x00000000__PTRDIFF_T XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"XPAR_PL_RAM_0_S_AXI_BASEADDR 0x40000000XPS_SMC_INT_ID 50XST_WDTTB_TIMER_FAILED 1251L__INT8_MAX__ 127XPAR_PS7_QSPI_0_BASEADDR 0xE000D000XPAR_XQSPIPS_NUM_INSTANCES 1__CS_SOURCERYGXX_MAJ__ 2013XREG_FPSCR_RMODE_BIT (22)_N 04__strfmonlike(fmtarg,firstvararg) __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))XREG_CP1 1UINTMAX_C(x) x ##ULLXST_FLASH_CFI_QUERY_ERROR 1138LXil_AssertVoid(Expression) { if (Expression) { Xil_AssertStatus = XIL_ASSERT_NONE; } else { Xil_Assert(__FILE__, __LINE__); Xil_AssertStatus = XIL_ASSERT_OCCURRED; return; } }XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000__SACCUM_FBIT__ 7__HQ_FBIT__ 15XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"__LLACCUM_IBIT__ 32XREG_GPR12 r12XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"_CAST_VOID (void)XUARTPS_MR_PARITY_EVEN 0x00000000__SIZE_T XST_NOT_POLLED 10L__lock_close_recursive(lock) (_CAST_VOID 0)__LDBL_DIG__ 15__CHAR32_TYPE__ long unsigned intXil_DisableNestedInterrupts() __asm__ __volatile__ ("ldmfd sp!, {lr}"); __asm__ __volatile__ ("msr cpsr_c, #0x92"); __asm__ __volatile__ ("ldmfd sp!, {lr}"); __asm__ __volatile__ ("msr spsr_cxsf, lr");XREG_CR11 cr11__Long long__pure2 __attribute__((__const__))__GCC_ATOMIC_SHORT_LOCK_FREE 2XUARTPS_MODEMSR_RI 0x00000040XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCDoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)__SIZEOF_POINTER__ 4INT_FAST32_MIN (-__STDINT_EXP(INT_MAX)-1)XUARTPS_FORMAT_1_5_STOP_BIT 1__pure __attribute__((__pure__))__ARM_SIZEOF_WCHAR_T 32XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID__UINTMAX_TYPE__ long long unsigned intXPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_IDXUartPs_GetChannelStatus(InstancePtr) Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET)XST_SYSACE_NO_LOCK 1351LXPAR_AXI_EMC __CONCAT1(x,y) x ## yUINT64_C(x) x ##ULLXPS_L2CC_BASEADDR 0xF8F02000XPS_QSPI_BASEADDR 0xE000D000XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF__GNUC_PREREQ(maj,min) ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))Xil_Htonl(Data) Xil_EndianSwap32(Data)XUARTPS_MODEMSR_DCD 0x00000080XUARTPS_MODEMSR_FCMS 0x00000100__FINITE_MATH_ONLY__ 0XPAR_XADCPS_0_HIGHADDR 0xF8007120XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE_T_WCHAR_ XST_IIC_DRR_READBACK_ERROR 1085_NOARGS voidXREG_FPSCR_DEFAULT_NAN (1 << 25)XUARTPS_MODEMSR_DCTS 0x00000001__LFRACT_MIN__ (-0.5LR-0.5LR)_B 0200XIL_COMPONENT_IS_READY 0x11111111XPAR_XUSBPS_0_BASEADDR 0xE0002000__RCSID_SOURCE(s) struct __hackXPAR_PS7_DMA_S_DEVICE_ID 1XPS_I2C1_BASEADDR 0xE0005000__GCC_ATOMIC_LLONG_LOCK_FREE 2XREG_CPSR_FIQ_MODE 0x11__ULFRACT_EPSILON__ 0x1P-32ULRXUARTPS_BAUDDIV_OFFSET 0x34_tolower(__c) ((unsigned char)(__c) - 'A' + 'a')XPS_GPIO_INT_ID 52UINT_FAST32_MAX (__STDINT_EXP(INT_MAX)*2U+1U)XUARTPS_MR_CHMODE_SHIFT 8XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"XREG_FPSCR_FLUSHTOZERO (1 << 24)XPAR_PS7_WDT_0_INTR XPS_WDT_INT_IDXREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"__NEWLIB_H__ 1baseaddrXIL_EXCEPTION_ID_FIRST 0XUartPs_DisableUart(InstancePtr) Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), (((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS)))XIL_ASSERT_NONE 0XPAR_XSDPS_0_HIGHADDR 0xE0100FFFXREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"XPS_TTC1_0_INT_ID 69XUARTPS_MR_CHMODE_ECHO 0x00000100__ULLACCUM_FBIT__ 32XREG_CR1 cr1_REENT_SIGNAL_BUF(ptr) ((ptr)->_new._reent._signal_buf)USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"__LDBL_HAS_QUIET_NAN__ 1__ARM_FEATURE_DSP 1__rangeof(type,start,end) (__offsetof(type, end) - __offsetof(type, start))XPAR_SCUTIMER_DEVICE_ID 0XUARTPS_RXTOUT_OFFSET 0x1C__NO_INLINE__ 1va_end(v) __builtin_va_end(v)_SYS_CDEFS_H_ XREG_CP15_CONTROL_I_BIT 0x00001000XUARTPS_CR_RX_EN 0x00000004__ULLACCUM_IBIT__ 32__DECONST(type,var) ((type)(uintptr_t)(const void *)(var))XPAR_XSCUTIMER_NUM_INSTANCES 1__PTRDIFF_MAX__ 2147483647XUARTPS_OPTION_SET_BREAK 0x0080__LDBL_MANT_DIG__ 53XPS_SYSMON_INT_ID 39XST_NAND_BUSY 1441L__ULLFRACT_FBIT__ 64XUARTPS_SR_TXFULL 0x00000010_EXFNPTR(name,proto) (* name) protoXPS_FPGA15_INT_ID 91XUARTPS_CR_STARTBRK 0x00000080__INT32_MAX__ 2147483647L_SIZE_T_DEFINED XUARTPS_MR_PARITY_MARK 0x00000018__CS_SOURCERYGXX_REV__ 46XPAR_XUARTPS_NUM_INSTANCES 1__UQQ_IBIT__ 0XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"___int8_t_defined 1XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ_Noreturn __dead2XPAR_PS7_TTC_2_BASEADDR 0XF8001008__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1__BSD_VISIBLE 1XREG_CR6 cr6XPS_DMA5_INT_ID 73XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFFXPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8XUARTPS_MODEMSR_DDSR 0x00000002XPAR_XUARTPS_1_INTR XPS_UART1_INT_IDXST_FLASH_BLOCKING_CALL_ERROR 1137LXST_HWICAP_WRITE_DONE 1421XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF__ACCUM_MIN__ (-0X1P15K-0X1P15K)__USFRACT_EPSILON__ 0x1P-8UHR__SCHAR_MAX__ 127XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"XUARTPS_FORMAT_2_STOP_BIT 2__ORDER_BIG_ENDIAN__ 4321XPAR_XADCPS_NUM_INSTANCES 1__UFRACT_MAX__ 0XFFFFP-16URXPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0_Z15test_peripheralm_MACHINE__DEFAULT_TYPES_H __UINT_FAST32_TYPE__ unsigned intBaseAddressXREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"PL_RAM_mWriteMemory(Address,Data) Xil_Out32(Address, (u32)(Data))XPS_FPGA12_INT_ID 88XPS_USB0_INT_ID 53XST_NO_FEATURE 19LXPAR_XUSBPS_1_INTR XPS_USB1_INT_IDXST_NAND_WRITE_PROTECTED 1451LXPAR_PS7_USB_0_DEVICE_ID 0XREG_MVFR0 c7Xil_EnableNestedInterrupts() __asm__ __volatile__ ("mrs lr, spsr"); __asm__ __volatile__ ("stmfd sp!, {lr}"); __asm__ __volatile__ ("msr cpsr_c, #0x1F"); __asm__ __volatile__ ("stmfd sp!, {lr}");__need_wchar_t__FLT_DECIMAL_DIG__ 9__INT32_TYPE__ long int_T_PTRDIFF XST_EMAC_MEMORY_ALLOC_ERROR 1002LXST_DEVICE_NOT_FOUND 2L__USACCUM_IBIT__ 8XIL_EXCEPTION_ID_IRQ_INT 5XREG_CP2 2XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"XST_UART_CONFIG_ERROR 1053L_READ_WRITE_RETURN_TYPE intXPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_IDXUARTPS_SR_TNFUL 0x00004000XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000_REENT_INIT_ATEXIT _NULL, _ATEXIT_INIT,XREG_FPSCR_ROUND_PLUSINF (1 << 22)XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID__UINTPTR_TYPE__ unsigned intXREG_FPSCR_V_BIT (1 << 28)XST_OPBARB_NOT_FIXED_PRIORITY 1179XREG_CPSR_C_BIT 0x20000000XPS_DDR_CTRL_BASEADDR 0xF8006000__LFRACT_FBIT__ 31XST_IIC_STAND_REG_RESET_ERROR 1079_SYS_SIZE_T_H XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"XPAR_XADCPS_0_BASEADDR 0xF8007100__STDC__ 1__int_least64_t_defined 1XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000_NOTHROW __attribute__ ((nothrow))XPS_SDIO0_BASEADDR 0xE0100000__END_DECLS }XPAR_XGPIOPS_NUM_INSTANCES 1_EXPARM(name,proto) (* name) proto__UINT16_MAX__ 65535mtcpsr(v) __asm__ __volatile__( "msr cpsr,%0\n" : : "r" (v) )__ARM_SIZEOF_MINIMAL_ENUM 1XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0__INT64_C(c) c ## LLXPAR_PS7_DMA_S_BASEADDR 0xF8003000XST_FR_BUF_LOCKED 1402XREG_FPSCR_LENGTH_BIT (16)__STDINT_EXP(x) __ ##x ##__XREG_MVFR0_SQRT_BIT (20)XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"__DA_FBIT__ 31XUARTPS_IXR_TTRIG 0x00000400SIZE_MAX __SIZE_MAX__XREG_CPSR_UNDEFINED_MODE 0x1BXPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FFXUARTPS_CR_EN_DIS_MASK 0x0000003C__XSTRING(x) __STRING(x)__SCCSID(s) struct __hack__GCC_ATOMIC_BOOL_LOCK_FREE 2__DEC64_MAX__ 9.999999999999999E384DD__ARM_ARCH_7A__ 1__WCHAR_MAX__ 4294967295UINT_LEAST16_MIN -32768XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000XST_FR_NO_BUF 1403WINT_MIN __WINT_MIN__XST_DMA_SG_NO_DATA 525LXST_UART __DA_IBIT__ 32__TQ_FBIT__ 127__VFP_FP__ 1XREG_CP15_CONTROL_B_BIT 0x00000080XREG_MVFR0_DP_BIT (8)XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_IDXPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID__INT_LEAST8_MAX__ 127_REENT_CHECK_MISC(ptr) XUARTPS_BAUDGEN_RESET_VAL 0x0000028B_WANT_IO_LONG_LONG 1XPS_GEM1_INT_ID 77__ULFRACT_IBIT__ 0XPAR_XDMAPS_0_BASEADDR 0xF8004000cpsief() __asm__ __volatile__("cpsie f\n")XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZXPAR_PS7_SPI_0_INTR XPS_SPI0_INT_IDXPS_FPGA4_INT_ID 65UINT_FAST8_MAX (__STDINT_EXP(INT_MAX)*2U+1U)XST_NO_CALLBACK 18LXPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID__ARM_NEON__ 1XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"__SIZEOF_DOUBLE__ 8__LDBL_MAX_EXP__ 1024XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_IDXPS_CAN1_INT_ID 83XREG_CR0 cr0XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115XUARTPS_CR_STOPBRK 0x00000100XREG_FPSCR_IXC (1 << 4)_BSD_WCHAR_T_ XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)XPS_SAM_RAM_BASEADDR 0xFFFC0000_RAND48_ADD (0x000b)XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ__scanflike(fmtarg,firstvararg) __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))XUARTPS_OPTION_STOP_BREAK 0x0040XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"INT16_MAX 32767__INT_FAST32_MAX__ 2147483647__LLACCUM_FBIT__ 31XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3XPS_DEV_CFG_APB_BASEADDR 0xF8007000_REENT_MP_FREELIST(ptr) ((ptr)->_freelist)__signed signed__DEPRECATED 1strb(adr,val) __asm__ __volatile__( "strb %0,[%1]\n" : : "r" (val), "r" (adr) )XUARTPS_MODEMCR_DTR 0x00000001_SYS_FEATURES_H XPAR_XTTCPS_0_BASEADDR 0xF8001000__arm__ 1XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"XUartPs_GetModeControl(InstancePtr) Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET)CallBackRefXPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFFXNULL NULLUINT_LEAST16_MAX 65535XPAR_PS7_XADC_0_DEVICE_ID 0XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFFXPS_SPI1_INT_ID 81test_address__ATOMIC_ACQ_REL 4DATA_SYNC dsb()XIL_EXCEPTION_ID_LAST 6_FVWRITE_IN_STREAMIO 1_SIZET_ __INT8_TYPE__ signed char__LDBL_DENORM_MIN__ 4.9406564584124654e-324LXUARTPS_FLOWDEL_OFFSET 0x38XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)XREG_FPSCR_ROUND_MINUSINF (2 << 22)XIL_COMPONENT_IS_STARTED 0x22222222_STDDEF_H_ __RAND_MAXXPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_IDXREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"__GNUC_PREREQ__(ma,mi) __GNUC_PREREQ(ma, mi)__ACCUM_MAX__ 0X7FFFFFFFP-15K__ARM_PCS 1__INT_FAST32_TYPE__ int__lock_init_recursive(lock) (_CAST_VOID 0)XPAR_XUARTPS_0_HAS_MODEM 0XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"XST_SPI_RECEIVE_OVERRUN 1154XREG_GPR15 r15__DEQUALIFY(type,var) ((type)(uintptr_t)(const volatile void *)(var))XPAR_PS7_UART_1_BASEADDR 0xE0001000XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFFINT_FAST64_MIN INT_LEAST64_MINXSTATUS_H XST_NAND_ALIGNMENT_ERROR 1448LXUartPs_IsTransmitEmpty(InstancePtr) ((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY)XPS_UART0_BASEADDR 0xE0000000XUARTPS_SR_OVER 0x00000020__ATTRIBUTE_IMPURE_PTR__ XPS_GEM0_WAKE_INT_ID 55__int_fast64_t_defined 1_S 010XREG_CP15_CONTROL_C_BIT 0x00000004XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFFXREG_CR15 cr15XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000_REENT_SIGNAL_SIZE 24XUARTPS_OPER_MODE_AUTO_ECHO 0x01__GNUC_GNU_INLINE__ 1XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"XPS_PARPORT_CRTL_BASEADDR 0xE000E000_BSD_PTRDIFF_T_ __WCHAR_T XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)XPAR_PS7_SCUWDT_0_DEVICE_ID 0XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"XREG_CP3 3__LACCUM_IBIT__ 32XIL_EXCEPTION_H XPS_GEM0_INT_ID 54__ULLFRACT_EPSILON__ 0x1P-64ULLRXPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8__DEC64_MIN__ 1E-383DDXST_DMA_SG_LIST_FULL 517L__INT16_C(c) c__THROW XPAR_PL_RAM_NUM_INSTANCES 1SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1)XST_DEVICE_IS_STOPPED 6LWCHAR_MIN __WCHAR_MIN____attribute_format_strfmon__(a,b) XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115__SIZEOF_SHORT__ 2XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZXREG_CR14 cr14UINTPTR_MAX __UINTPTR_MAX____have_long32 1XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"XPAR_XSPIPS_1_INTR XPS_SPI1_INT_IDXUARTPS_FORMAT_6_BITS 3XUARTPS_SR_FRAME 0x00000040XPS_FPGA11_INT_ID 87XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061FXil_ExceptionDisableMask(Mask) mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))XUARTPS_FORMAT_SPACE_PARITY 2__ULFRACT_MIN__ 0.0ULR_REENT_WCRTOMB_STATE(ptr) ((ptr)->_new._reent._wcrtomb_state)XPS_CORE_PARITY1_INT_ID 33XPAR_PS7_UART_1_DEVICE_ID 0__UINT64_MAX__ 18446744073709551615ULL_REENT_SMALL_CHECK_INIT(ptr) __need_wint_t XREG_CR13 cr13XPAR_PS7_UART_1_HIGHADDR 0xE0001FFFXST_IPIF_DEVICE_STATUS_ERROR 533LXPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8_T_SIZE XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)INT32_MAX 2147483647LXPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FFXIL_EXCEPTION_ID_RESET 0XPSEUDO_ASM_GCC_H INT64_C(x) x ##LLXPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000)__SFRACT_EPSILON__ 0x1P-7HR__ATOMIC_CONSUME 1__unused __attribute__((__unused__))__FLT_MIN__ 1.1754943508222875e-38F__INT_LEAST16_TYPE__ short intXST_EMAC_OUT_OF_BUFFERS 1005L__INTMAX_MAX__ 9223372036854775807LLXREG_CP15 15__USFRACT_FBIT__ 8cpsiei() __asm__ __volatile__("cpsie i\n")XPAR_XSCUGIC_NUM_INSTANCES 1XST_UART_TEST_FAIL 1054LXUARTPS_FORMAT_7_BITS 2__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2__LLFRACT_FBIT__ 63__SIZEOF_PTRDIFF_T__ 4__restrict _REENT_TM(ptr) (&(ptr)->_new._reent._localtime_buf)XST_IPIF_IP_ENABLE_ERROR 538LXil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)/home/mwerner/Projekte/MEMSEC/HW/HW.sdk/test/DebugINT16_MIN -32768XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF_ATTRIBUTE(attrs) __attribute__ (attrs)XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF_VA_LIST_T_H XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDRXST_DMA_ERROR 9LXST_IPIF_DEVICE_PENDING_ERROR 539LXUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS__UINT_LEAST16_MAX__ 65535XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF__DBL_MIN_EXP__ (-1021)__exported __attribute__((__visibility__("default")))XStatusXST_IIC_GENERAL_CALL_ADDRESS 1078XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"XST_DEVICE_BUSY 21L_REENT_MBRLEN_STATE(ptr) ((ptr)->_new._reent._mbrlen_state)XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_IDXREG_CR3 cr3XREG_CR8 cr8UINT_LEAST32_MAX 4294967295UL__CC_SUPPORTS___INLINE__ 1XREG_CP15_CONTROL_A_BIT 0x00000002__CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1XPAR_PS7_ETHERNET_0_DEVICE_ID 0XST_IS_STARTED 23LXST_FLASH_ALIGNMENT_ERROR 1136L__LDBL_MAX_10_EXP__ 308Mem32ValueINT_LEAST64_MAX 9223372036854775807LL__IMPORT ___int32_t_defined 1XPAR_XEMACPS_0_HIGHADDR 0xE000BFFFXUARTPS_FORMAT_8_BITS 0__INT64_TYPE__ long long intINT_FAST8_MAX __STDINT_EXP(INT_MAX)XUARTPS_OPTION_SET_FCM 0x0001__DBL_DENORM_MIN__ double(4.9406564584124654e-324L)__TA_FBIT__ 63__DEC32_MAX__ 9.999999E96DFXPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000XST_SPI_SLAVE_MODE_FAULT 1159__malloc_like __attribute__((__malloc__))___int_ptrdiff_t_h __lock_try_acquire_recursive(lock) (_CAST_VOID 0)INT8_MIN -128__UINT_LEAST32_TYPE__ long unsigned int__SHRT_MAX__ 32767_NOINLINE_STATIC _NOINLINE staticXPAR_SCUWDT_DEVICE_ID 0_LONG_DOUBLE long doubleXREG_CP13 13XREG_CPSR_MODE_BITS 0x1FSTDIN_BASEADDRESS 0xE0001000__HA_IBIT__ 8__TA_IBIT__ 64_ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115_P 020XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF__ATOMIC_RELEASE 3__HQ_IBIT__ 0XUARTPS_CR_RX_DIS 0x00000008XREG_CPSR_IRQ_ENABLE 0x80__SA_IBIT__ 16XUARTPS_MODEMSR_OFFSET 0x28XUARTPS_BAUDGEN_MASK 0x0000FFFF__COPYRIGHT(s) struct __hack_WIDE_ORIENT 1XUARTPS_CR_OFFSET 0x00__UHA_FBIT__ 8XST_EMAC_MII_BUSY 1004LXREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"XST_RECV_ERROR 27LXREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"XPS_TTC1_1_INT_ID 70__DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL__ARM_FEATURE_CLZ 1XST_IPIF_ERROR 541LXREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"__UINT8_MAX__ 255__ARM_FEATURE_LDREX 15XREG_FPEXC c8XUARTPS_EVENT_RECV_DATA 1XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"XPS_IOU_BUS_CFG_BASEADDR 0xE0200000XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_IDXREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID__DEC32_MIN_EXP__ (-94)__ULACCUM_EPSILON__ 0x1P-32ULKtest_peripheral_REENT_CHECK_TM(ptr) INT8_MAX 127XPS_DVC_INT_ID 40SYNCHRONIZE_IO dmb()__ARM_ARCH 7XIL_CACHE_H str(adr,val) __asm__ __volatile__( "str %0,[%1]\n" : : "r" (val), "r" (adr) )__CONCAT(x,y) __CONCAT1(x,y)XUARTPS_OPER_MODE_NORMAL 0x00__DBL_HAS_QUIET_NAN__ 1__LDBL_MIN_10_EXP__ (-307)stringify(s) tostring(s)__DEC32_MANT_DIG__ 7XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"XREG_CP4 4__UINTPTR_MAX__ 4294967295U__USFRACT_IBIT__ 0XST_REGISTER_ERROR 14LXREG_CPSR cpsr_REENT_ASCTIME_SIZE 26__DEC_EVAL_METHOD__ 2XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF__LDBL_HAS_INFINITY__ 1XREG_CP11 11XUARTPS_FORMAT_NO_PARITY 4_FSEEK_OPTIMIZATION 1__GXX_WEAK__ 1XPAR_XSDPS_NUM_INSTANCES 1XPAR_XUARTPS_0_INTR XPS_UART0_INT_IDXST_DMA_RESET_REGISTER_ERROR 512LXPS_UART0_INT_ID 59XST_USB_BUF_ALIGN_ERROR 1411XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSRXREG_CR5 cr5__UINT_FAST32_MAX__ 4294967295U__SIZEOF_LONG_DOUBLE__ 8XUARTPS_OPTION_ASSERT_DTR 0x0002XUARTPS_SR_TXEMPTY 0x0000000813XUartPsBufferXil_Out32LE(Addr,Value) Xil_Out32(Addr, Value)XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600XPS_ECC_INT_ID 36__FLT_HAS_DENORM__ 1__GNUCLIKE_MATH_BUILTIN_CONSTANTS INT32_C(x) x ##LXPS_TTC1_2_INT_ID 71XPS_PARPORT1_BASEADDR 0xE4000000XPS_GEM0_BASEADDR 0xE000B000XPAR_XEMACPS_0_BASEADDR 0xE000B000XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF___Static_assert(x,y) typedef char __assert_ ## y[(x) ? 1 : -1]XUARTPS_FORMAT_EVEN_PARITY 0UINT16_C(x) x__TQ_IBIT__ 0XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_IDXPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000XREG_GPR13 r13__SIZEOF_FLOAT__ 4mainXPAR_GLOBAL_TMR_DEVICE_ID 0__SIZE_T__ __SIZE_TYPE__ unsigned intXST_FAILURE 1Lcpsidf() __asm__ __volatile__("cpsid f\n")XST_FLASH_TIMEOUT_ERROR 1134L_Alignof(x) __alignof(x)__offsetof(type,field) offsetof(type, field)XST_IIC_RX_FIFO_REG_RESET_ERROR 1081__UINT_LEAST8_TYPE__ unsigned char_RAND48_SEED_1 (0xabcd)XST_NAND_PARAM_PAGE_ERROR 1449LXREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID__STRING(x) #xXPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000_ELIDABLE_INLINE extern __inline__ _ATTRIBUTE ((__always_inline__))XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID__CHAR16_TYPE__ short unsigned intXPAR_XSLCR_NUM_INSTANCES 1__UFRACT_FBIT__ 16INT64_MAX 9223372036854775807LLXUARTPS_MR_CHARLEN_SHIFT 1XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"XST_EMAC_MII_READ_ERROR 1003LXST_SPI_SLAVE_MODE 1160XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"XREG_CPSR_USER_MODE 0x10XPAR_XSCUWDT_NUM_INSTANCES 1INT_LEAST8_MAX 127XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"XREG_FPINST2 c10XST_PCI_INVALID_ADDRESS 1361LXREG_MVFR0_EXEC_TRAP_BIT (12)NextBytePtrXUARTPS_SR_FLOWDEL 0x00001000XST_FLASH_WRITE_SUSPENDED 1130LXPS_OCM_BASEADDR 0xF800C000_MACHINE__TYPES_H XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_IDXUARTPS_MR_CHMODE_MASK 0x00000300UINT32_MAX 4294967295ULXil_ExceptionEnableMask(Mask) mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))PL_RAM_mReadMemory(Address) Xil_In32(Address)INTMAX_MAX __INTMAX_MAX__XPS_I2C0_INT_ID 57XST_FLASH_PART_NOT_SUPPORTED 1131L__UINT_LEAST16_TYPE__ short unsigned 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