1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34 #include "en/port.h"
35 #include "en/xsk/pool.h"
36 #include "lib/clock.h"
37
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)38 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
40 {
41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
44 strlcpy(drvinfo->version, DRIVER_VERSION,
45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
47 "%d.%d.%04d (%.16s)",
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 mdev->board_id);
50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
51 sizeof(drvinfo->bus_info));
52 }
53
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)54 static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
56 {
57 struct mlx5e_priv *priv = netdev_priv(dev);
58
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60 }
61
62 struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
65 };
66
67 static
68 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69 static
70 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
71
72 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
73 ({ \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
87 } \
88 })
89
mlx5e_build_ptys2ethtool_map(void)90 void mlx5e_build_ptys2ethtool_map(void)
91 {
92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ext,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
197 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
198 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
199 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
200 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
201 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
202 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
203 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
204 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
205 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
206 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
207 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
208 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
209 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
210 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
211 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
212 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
213 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
214 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
215 }
216
mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev * mdev,struct ptys2ethtool_config ** arr,u32 * size)217 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
218 struct ptys2ethtool_config **arr,
219 u32 *size)
220 {
221 bool ext = mlx5e_ptys_ext_supported(mdev);
222
223 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
224 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
225 ARRAY_SIZE(ptys2legacy_ethtool_table);
226 }
227
228 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
229
230 struct pflag_desc {
231 char name[ETH_GSTRING_LEN];
232 mlx5e_pflag_handler handler;
233 };
234
235 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
236
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)237 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
238 {
239 switch (sset) {
240 case ETH_SS_STATS:
241 return mlx5e_stats_total_num(priv);
242 case ETH_SS_PRIV_FLAGS:
243 return MLX5E_NUM_PFLAGS;
244 case ETH_SS_TEST:
245 return mlx5e_self_test_num(priv);
246 default:
247 return -EOPNOTSUPP;
248 }
249 }
250
mlx5e_get_sset_count(struct net_device * dev,int sset)251 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
252 {
253 struct mlx5e_priv *priv = netdev_priv(dev);
254
255 return mlx5e_ethtool_get_sset_count(priv, sset);
256 }
257
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)258 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
259 {
260 int i;
261
262 switch (stringset) {
263 case ETH_SS_PRIV_FLAGS:
264 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
265 strcpy(data + i * ETH_GSTRING_LEN,
266 mlx5e_priv_flags[i].name);
267 break;
268
269 case ETH_SS_TEST:
270 for (i = 0; i < mlx5e_self_test_num(priv); i++)
271 strcpy(data + i * ETH_GSTRING_LEN,
272 mlx5e_self_tests[i]);
273 break;
274
275 case ETH_SS_STATS:
276 mlx5e_stats_fill_strings(priv, data);
277 break;
278 }
279 }
280
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)281 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
282 {
283 struct mlx5e_priv *priv = netdev_priv(dev);
284
285 mlx5e_ethtool_get_strings(priv, stringset, data);
286 }
287
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)288 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
289 struct ethtool_stats *stats, u64 *data)
290 {
291 int idx = 0;
292
293 mutex_lock(&priv->state_lock);
294 mlx5e_stats_update(priv);
295 mutex_unlock(&priv->state_lock);
296
297 mlx5e_stats_fill(priv, data, idx);
298 }
299
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)300 static void mlx5e_get_ethtool_stats(struct net_device *dev,
301 struct ethtool_stats *stats,
302 u64 *data)
303 {
304 struct mlx5e_priv *priv = netdev_priv(dev);
305
306 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
307 }
308
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)309 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
310 struct ethtool_ringparam *param)
311 {
312 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
313 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
314 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
315 param->tx_pending = 1 << priv->channels.params.log_sq_size;
316 }
317
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param)318 static void mlx5e_get_ringparam(struct net_device *dev,
319 struct ethtool_ringparam *param)
320 {
321 struct mlx5e_priv *priv = netdev_priv(dev);
322
323 mlx5e_ethtool_get_ringparam(priv, param);
324 }
325
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)326 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
327 struct ethtool_ringparam *param)
328 {
329 struct mlx5e_channels new_channels = {};
330 u8 log_rq_size;
331 u8 log_sq_size;
332 int err = 0;
333
334 if (param->rx_jumbo_pending) {
335 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
336 __func__);
337 return -EINVAL;
338 }
339 if (param->rx_mini_pending) {
340 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
341 __func__);
342 return -EINVAL;
343 }
344
345 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
346 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
347 __func__, param->rx_pending,
348 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
349 return -EINVAL;
350 }
351
352 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
353 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
354 __func__, param->tx_pending,
355 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
356 return -EINVAL;
357 }
358
359 log_rq_size = order_base_2(param->rx_pending);
360 log_sq_size = order_base_2(param->tx_pending);
361
362 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
363 log_sq_size == priv->channels.params.log_sq_size)
364 return 0;
365
366 mutex_lock(&priv->state_lock);
367
368 new_channels.params = priv->channels.params;
369 new_channels.params.log_rq_mtu_frames = log_rq_size;
370 new_channels.params.log_sq_size = log_sq_size;
371
372 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
373 priv->channels.params = new_channels.params;
374 goto unlock;
375 }
376
377 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
378
379 unlock:
380 mutex_unlock(&priv->state_lock);
381
382 return err;
383 }
384
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param)385 static int mlx5e_set_ringparam(struct net_device *dev,
386 struct ethtool_ringparam *param)
387 {
388 struct mlx5e_priv *priv = netdev_priv(dev);
389
390 return mlx5e_ethtool_set_ringparam(priv, param);
391 }
392
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)393 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
394 struct ethtool_channels *ch)
395 {
396 mutex_lock(&priv->state_lock);
397
398 ch->max_combined = priv->max_nch;
399 ch->combined_count = priv->channels.params.num_channels;
400 if (priv->xsk.refcnt) {
401 /* The upper half are XSK queues. */
402 ch->max_combined *= 2;
403 ch->combined_count *= 2;
404 }
405
406 mutex_unlock(&priv->state_lock);
407 }
408
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)409 static void mlx5e_get_channels(struct net_device *dev,
410 struct ethtool_channels *ch)
411 {
412 struct mlx5e_priv *priv = netdev_priv(dev);
413
414 mlx5e_ethtool_get_channels(priv, ch);
415 }
416
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)417 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
418 struct ethtool_channels *ch)
419 {
420 struct mlx5e_params *cur_params = &priv->channels.params;
421 unsigned int count = ch->combined_count;
422 struct mlx5e_channels new_channels = {};
423 bool arfs_enabled;
424 int err = 0;
425
426 if (!count) {
427 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
428 __func__);
429 return -EINVAL;
430 }
431
432 if (cur_params->num_channels == count)
433 return 0;
434
435 mutex_lock(&priv->state_lock);
436
437 /* Don't allow changing the number of channels if there is an active
438 * XSK, because the numeration of the XSK and regular RQs will change.
439 */
440 if (priv->xsk.refcnt) {
441 err = -EINVAL;
442 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
443 __func__);
444 goto out;
445 }
446
447 new_channels.params = *cur_params;
448 new_channels.params.num_channels = count;
449
450 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
451 struct mlx5e_params old_params;
452
453 old_params = *cur_params;
454 *cur_params = new_channels.params;
455 err = mlx5e_num_channels_changed(priv);
456 if (err)
457 *cur_params = old_params;
458
459 goto out;
460 }
461
462 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
463 if (arfs_enabled)
464 mlx5e_arfs_disable(priv);
465
466 /* Switch to new channels, set new parameters and close old ones */
467 err = mlx5e_safe_switch_channels(priv, &new_channels,
468 mlx5e_num_channels_changed_ctx, NULL);
469
470 if (arfs_enabled) {
471 int err2 = mlx5e_arfs_enable(priv);
472
473 if (err2)
474 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
475 __func__, err2);
476 }
477
478 out:
479 mutex_unlock(&priv->state_lock);
480
481 return err;
482 }
483
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)484 static int mlx5e_set_channels(struct net_device *dev,
485 struct ethtool_channels *ch)
486 {
487 struct mlx5e_priv *priv = netdev_priv(dev);
488
489 return mlx5e_ethtool_set_channels(priv, ch);
490 }
491
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)492 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
493 struct ethtool_coalesce *coal)
494 {
495 struct dim_cq_moder *rx_moder, *tx_moder;
496
497 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
498 return -EOPNOTSUPP;
499
500 rx_moder = &priv->channels.params.rx_cq_moderation;
501 coal->rx_coalesce_usecs = rx_moder->usec;
502 coal->rx_max_coalesced_frames = rx_moder->pkts;
503 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
504
505 tx_moder = &priv->channels.params.tx_cq_moderation;
506 coal->tx_coalesce_usecs = tx_moder->usec;
507 coal->tx_max_coalesced_frames = tx_moder->pkts;
508 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
509
510 return 0;
511 }
512
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal)513 static int mlx5e_get_coalesce(struct net_device *netdev,
514 struct ethtool_coalesce *coal)
515 {
516 struct mlx5e_priv *priv = netdev_priv(netdev);
517
518 return mlx5e_ethtool_get_coalesce(priv, coal);
519 }
520
521 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
522 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
523
524 static void
mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)525 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
526 {
527 struct mlx5_core_dev *mdev = priv->mdev;
528 int tc;
529 int i;
530
531 for (i = 0; i < priv->channels.num; ++i) {
532 struct mlx5e_channel *c = priv->channels.c[i];
533
534 for (tc = 0; tc < c->num_tc; tc++) {
535 mlx5_core_modify_cq_moderation(mdev,
536 &c->sq[tc].cq.mcq,
537 coal->tx_coalesce_usecs,
538 coal->tx_max_coalesced_frames);
539 }
540 }
541 }
542
543 static void
mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)544 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
545 {
546 struct mlx5_core_dev *mdev = priv->mdev;
547 int i;
548
549 for (i = 0; i < priv->channels.num; ++i) {
550 struct mlx5e_channel *c = priv->channels.c[i];
551
552 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
553 coal->rx_coalesce_usecs,
554 coal->rx_max_coalesced_frames);
555 }
556 }
557
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)558 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
559 struct ethtool_coalesce *coal)
560 {
561 struct dim_cq_moder *rx_moder, *tx_moder;
562 struct mlx5_core_dev *mdev = priv->mdev;
563 struct mlx5e_channels new_channels = {};
564 bool reset_rx, reset_tx;
565 int err = 0;
566
567 if (!MLX5_CAP_GEN(mdev, cq_moderation))
568 return -EOPNOTSUPP;
569
570 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
571 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
572 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
573 __func__, MLX5E_MAX_COAL_TIME);
574 return -ERANGE;
575 }
576
577 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
578 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
579 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
580 __func__, MLX5E_MAX_COAL_FRAMES);
581 return -ERANGE;
582 }
583
584 mutex_lock(&priv->state_lock);
585 new_channels.params = priv->channels.params;
586
587 rx_moder = &new_channels.params.rx_cq_moderation;
588 rx_moder->usec = coal->rx_coalesce_usecs;
589 rx_moder->pkts = coal->rx_max_coalesced_frames;
590 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
591
592 tx_moder = &new_channels.params.tx_cq_moderation;
593 tx_moder->usec = coal->tx_coalesce_usecs;
594 tx_moder->pkts = coal->tx_max_coalesced_frames;
595 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
596
597 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
598 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
599
600 if (reset_rx) {
601 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
602 MLX5E_PFLAG_RX_CQE_BASED_MODER);
603
604 mlx5e_reset_rx_moderation(&new_channels.params, mode);
605 }
606 if (reset_tx) {
607 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
608 MLX5E_PFLAG_TX_CQE_BASED_MODER);
609
610 mlx5e_reset_tx_moderation(&new_channels.params, mode);
611 }
612
613 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
614 priv->channels.params = new_channels.params;
615 goto out;
616 }
617
618 if (!reset_rx && !reset_tx) {
619 if (!coal->use_adaptive_rx_coalesce)
620 mlx5e_set_priv_channels_rx_coalesce(priv, coal);
621 if (!coal->use_adaptive_tx_coalesce)
622 mlx5e_set_priv_channels_tx_coalesce(priv, coal);
623 priv->channels.params = new_channels.params;
624 goto out;
625 }
626
627 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
628
629 out:
630 mutex_unlock(&priv->state_lock);
631 return err;
632 }
633
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal)634 static int mlx5e_set_coalesce(struct net_device *netdev,
635 struct ethtool_coalesce *coal)
636 {
637 struct mlx5e_priv *priv = netdev_priv(netdev);
638
639 return mlx5e_ethtool_set_coalesce(priv, coal);
640 }
641
ptys2ethtool_supported_link(struct mlx5_core_dev * mdev,unsigned long * supported_modes,u32 eth_proto_cap)642 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
643 unsigned long *supported_modes,
644 u32 eth_proto_cap)
645 {
646 unsigned long proto_cap = eth_proto_cap;
647 struct ptys2ethtool_config *table;
648 u32 max_size;
649 int proto;
650
651 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
652 for_each_set_bit(proto, &proto_cap, max_size)
653 bitmap_or(supported_modes, supported_modes,
654 table[proto].supported,
655 __ETHTOOL_LINK_MODE_MASK_NBITS);
656 }
657
ptys2ethtool_adver_link(unsigned long * advertising_modes,u32 eth_proto_cap,bool ext)658 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
659 u32 eth_proto_cap, bool ext)
660 {
661 unsigned long proto_cap = eth_proto_cap;
662 struct ptys2ethtool_config *table;
663 u32 max_size;
664 int proto;
665
666 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
667 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
668 ARRAY_SIZE(ptys2legacy_ethtool_table);
669
670 for_each_set_bit(proto, &proto_cap, max_size)
671 bitmap_or(advertising_modes, advertising_modes,
672 table[proto].advertised,
673 __ETHTOOL_LINK_MODE_MASK_NBITS);
674 }
675
676 static const u32 pplm_fec_2_ethtool[] = {
677 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
678 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
679 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
680 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
681 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
682 };
683
pplm2ethtool_fec(u_long fec_mode,unsigned long size)684 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
685 {
686 int mode = 0;
687
688 if (!fec_mode)
689 return ETHTOOL_FEC_AUTO;
690
691 mode = find_first_bit(&fec_mode, size);
692
693 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
694 return pplm_fec_2_ethtool[mode];
695
696 return 0;
697 }
698
699 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
700 do { \
701 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
702 __set_bit(ethtool_fec, \
703 link_ksettings->link_modes.supported);\
704 } while (0)
705
706 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
707 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
708 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
709 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
710 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
711 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
712 };
713
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)714 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
715 struct ethtool_link_ksettings *link_ksettings)
716 {
717 unsigned long active_fec_long;
718 u32 active_fec;
719 u32 bitn;
720 int err;
721
722 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
723 if (err)
724 return (err == -EOPNOTSUPP) ? 0 : err;
725
726 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
727 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
728 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
729 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
730 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
731 ETHTOOL_LINK_MODE_FEC_RS_BIT);
732 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
733 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
734
735 active_fec_long = active_fec;
736 /* active fec is a bit set, find out which bit is set and
737 * advertise the corresponding ethtool bit
738 */
739 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
740 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
741 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
742 link_ksettings->link_modes.advertising);
743
744 return 0;
745 }
746
ptys2ethtool_supported_advertised_port(struct mlx5_core_dev * mdev,struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type)747 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev,
748 struct ethtool_link_ksettings *link_ksettings,
749 u32 eth_proto_cap, u8 connector_type)
750 {
751 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) {
752 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
753 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
754 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
755 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
756 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
757 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
758 ethtool_link_ksettings_add_link_mode(link_ksettings,
759 supported,
760 FIBRE);
761 ethtool_link_ksettings_add_link_mode(link_ksettings,
762 advertising,
763 FIBRE);
764 }
765
766 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
767 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
768 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
769 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
770 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
771 ethtool_link_ksettings_add_link_mode(link_ksettings,
772 supported,
773 Backplane);
774 ethtool_link_ksettings_add_link_mode(link_ksettings,
775 advertising,
776 Backplane);
777 }
778 return;
779 }
780
781 switch (connector_type) {
782 case MLX5E_PORT_TP:
783 ethtool_link_ksettings_add_link_mode(link_ksettings,
784 supported, TP);
785 ethtool_link_ksettings_add_link_mode(link_ksettings,
786 advertising, TP);
787 break;
788 case MLX5E_PORT_AUI:
789 ethtool_link_ksettings_add_link_mode(link_ksettings,
790 supported, AUI);
791 ethtool_link_ksettings_add_link_mode(link_ksettings,
792 advertising, AUI);
793 break;
794 case MLX5E_PORT_BNC:
795 ethtool_link_ksettings_add_link_mode(link_ksettings,
796 supported, BNC);
797 ethtool_link_ksettings_add_link_mode(link_ksettings,
798 advertising, BNC);
799 break;
800 case MLX5E_PORT_MII:
801 ethtool_link_ksettings_add_link_mode(link_ksettings,
802 supported, MII);
803 ethtool_link_ksettings_add_link_mode(link_ksettings,
804 advertising, MII);
805 break;
806 case MLX5E_PORT_FIBRE:
807 ethtool_link_ksettings_add_link_mode(link_ksettings,
808 supported, FIBRE);
809 ethtool_link_ksettings_add_link_mode(link_ksettings,
810 advertising, FIBRE);
811 break;
812 case MLX5E_PORT_DA:
813 ethtool_link_ksettings_add_link_mode(link_ksettings,
814 supported, Backplane);
815 ethtool_link_ksettings_add_link_mode(link_ksettings,
816 advertising, Backplane);
817 break;
818 case MLX5E_PORT_NONE:
819 case MLX5E_PORT_OTHER:
820 default:
821 break;
822 }
823 }
824
get_speed_duplex(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)825 static void get_speed_duplex(struct net_device *netdev,
826 u32 eth_proto_oper, bool force_legacy,
827 u16 data_rate_oper,
828 struct ethtool_link_ksettings *link_ksettings)
829 {
830 struct mlx5e_priv *priv = netdev_priv(netdev);
831 u32 speed = SPEED_UNKNOWN;
832 u8 duplex = DUPLEX_UNKNOWN;
833
834 if (!netif_carrier_ok(netdev))
835 goto out;
836
837 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
838 if (!speed) {
839 if (data_rate_oper)
840 speed = 100 * data_rate_oper;
841 else
842 speed = SPEED_UNKNOWN;
843 goto out;
844 }
845
846 duplex = DUPLEX_FULL;
847
848 out:
849 link_ksettings->base.speed = speed;
850 link_ksettings->base.duplex = duplex;
851 }
852
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)853 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
854 struct ethtool_link_ksettings *link_ksettings)
855 {
856 unsigned long *supported = link_ksettings->link_modes.supported;
857 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
858
859 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
860 }
861
get_advertising(u32 eth_proto_cap,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)862 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
863 struct ethtool_link_ksettings *link_ksettings,
864 bool ext)
865 {
866 unsigned long *advertising = link_ksettings->link_modes.advertising;
867 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
868
869 if (rx_pause)
870 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
871 if (tx_pause ^ rx_pause)
872 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
873 }
874
875 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
876 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
877 [MLX5E_PORT_NONE] = PORT_NONE,
878 [MLX5E_PORT_TP] = PORT_TP,
879 [MLX5E_PORT_AUI] = PORT_AUI,
880 [MLX5E_PORT_BNC] = PORT_BNC,
881 [MLX5E_PORT_MII] = PORT_MII,
882 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
883 [MLX5E_PORT_DA] = PORT_DA,
884 [MLX5E_PORT_OTHER] = PORT_OTHER,
885 };
886
get_connector_port(struct mlx5_core_dev * mdev,u32 eth_proto,u8 connector_type)887 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type)
888 {
889 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
890 return ptys2connector_type[connector_type];
891
892 if (eth_proto &
893 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
894 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
895 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
896 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
897 return PORT_FIBRE;
898 }
899
900 if (eth_proto &
901 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
902 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
903 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
904 return PORT_DA;
905 }
906
907 if (eth_proto &
908 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
909 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
910 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
911 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
912 return PORT_NONE;
913 }
914
915 return PORT_OTHER;
916 }
917
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)918 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
919 struct ethtool_link_ksettings *link_ksettings)
920 {
921 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
922 bool ext = mlx5e_ptys_ext_supported(mdev);
923
924 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
925 }
926
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)927 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
928 struct ethtool_link_ksettings *link_ksettings)
929 {
930 struct mlx5_core_dev *mdev = priv->mdev;
931 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
932 u32 eth_proto_admin;
933 u8 an_disable_admin;
934 u16 data_rate_oper;
935 u32 eth_proto_oper;
936 u32 eth_proto_cap;
937 u8 connector_type;
938 u32 rx_pause = 0;
939 u32 tx_pause = 0;
940 u32 eth_proto_lp;
941 bool admin_ext;
942 u8 an_status;
943 bool ext;
944 int err;
945
946 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
947 if (err) {
948 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
949 __func__, err);
950 goto err_query_regs;
951 }
952 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
953 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
954 eth_proto_capability);
955 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
956 eth_proto_admin);
957 /* Fields: eth_proto_admin and ext_eth_proto_admin are
958 * mutually exclusive. Hence try reading legacy advertising
959 * when extended advertising is zero.
960 * admin_ext indicates which proto_admin (ext vs. legacy)
961 * should be read and interpreted
962 */
963 admin_ext = ext;
964 if (ext && !eth_proto_admin) {
965 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
966 eth_proto_admin);
967 admin_ext = false;
968 }
969
970 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
971 eth_proto_oper);
972 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
973 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
974 an_status = MLX5_GET(ptys_reg, out, an_status);
975 connector_type = MLX5_GET(ptys_reg, out, connector_type);
976 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
977
978 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
979
980 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
981 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
982
983 get_supported(mdev, eth_proto_cap, link_ksettings);
984 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
985 admin_ext);
986 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
987 data_rate_oper, link_ksettings);
988
989 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
990 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ?
991 connector_type : MLX5E_PORT_UNKNOWN;
992 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type);
993 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin,
994 connector_type);
995 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
996
997 if (an_status == MLX5_AN_COMPLETE)
998 ethtool_link_ksettings_add_link_mode(link_ksettings,
999 lp_advertising, Autoneg);
1000
1001 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1002 AUTONEG_ENABLE;
1003 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1004 Autoneg);
1005
1006 err = get_fec_supported_advertised(mdev, link_ksettings);
1007 if (err) {
1008 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
1009 __func__, err);
1010 err = 0; /* don't fail caps query because of FEC error */
1011 }
1012
1013 if (!an_disable_admin)
1014 ethtool_link_ksettings_add_link_mode(link_ksettings,
1015 advertising, Autoneg);
1016
1017 err_query_regs:
1018 return err;
1019 }
1020
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1021 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1022 struct ethtool_link_ksettings *link_ksettings)
1023 {
1024 struct mlx5e_priv *priv = netdev_priv(netdev);
1025
1026 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1027 }
1028
mlx5e_speed_validate(struct net_device * netdev,bool ext,const unsigned long link_modes,u8 autoneg)1029 static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
1030 const unsigned long link_modes, u8 autoneg)
1031 {
1032 /* Extended link-mode has no speed limitations. */
1033 if (ext)
1034 return 0;
1035
1036 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1037 autoneg != AUTONEG_ENABLE) {
1038 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
1039 __func__);
1040 return -EINVAL;
1041 }
1042 return 0;
1043 }
1044
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1045 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1046 {
1047 u32 i, ptys_modes = 0;
1048
1049 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1050 if (*ptys2legacy_ethtool_table[i].advertised == 0)
1051 continue;
1052 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1053 link_modes,
1054 __ETHTOOL_LINK_MODE_MASK_NBITS))
1055 ptys_modes |= MLX5E_PROT_MASK(i);
1056 }
1057
1058 return ptys_modes;
1059 }
1060
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1061 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1062 {
1063 u32 i, ptys_modes = 0;
1064 unsigned long modes[2];
1065
1066 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1067 if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
1068 ptys2ext_ethtool_table[i].advertised[1] == 0)
1069 continue;
1070 memset(modes, 0, sizeof(modes));
1071 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1072 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1073
1074 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1075 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1076 ptys_modes |= MLX5E_PROT_MASK(i);
1077 }
1078 return ptys_modes;
1079 }
1080
ext_link_mode_requested(const unsigned long * adver)1081 static bool ext_link_mode_requested(const unsigned long *adver)
1082 {
1083 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1084 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1085 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1086
1087 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1088 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1089 }
1090
ext_requested(u8 autoneg,const unsigned long * adver,bool ext_supported)1091 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1092 {
1093 bool ext_link_mode = ext_link_mode_requested(adver);
1094
1095 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1096 }
1097
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1098 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1099 const struct ethtool_link_ksettings *link_ksettings)
1100 {
1101 struct mlx5_core_dev *mdev = priv->mdev;
1102 struct mlx5e_port_eth_proto eproto;
1103 const unsigned long *adver;
1104 bool an_changes = false;
1105 u8 an_disable_admin;
1106 bool ext_supported;
1107 u8 an_disable_cap;
1108 bool an_disable;
1109 u32 link_modes;
1110 u8 an_status;
1111 u8 autoneg;
1112 u32 speed;
1113 bool ext;
1114 int err;
1115
1116 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1117
1118 adver = link_ksettings->link_modes.advertising;
1119 autoneg = link_ksettings->base.autoneg;
1120 speed = link_ksettings->base.speed;
1121
1122 ext_supported = mlx5e_ptys_ext_supported(mdev);
1123 ext = ext_requested(autoneg, adver, ext_supported);
1124 if (!ext_supported && ext)
1125 return -EOPNOTSUPP;
1126
1127 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1128 mlx5e_ethtool2ptys_adver_link;
1129 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1130 if (err) {
1131 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1132 __func__, err);
1133 goto out;
1134 }
1135 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1136 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1137
1138 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
1139 if (err)
1140 goto out;
1141
1142 link_modes = link_modes & eproto.cap;
1143 if (!link_modes) {
1144 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1145 __func__);
1146 err = -EINVAL;
1147 goto out;
1148 }
1149
1150 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1151 &an_disable_admin);
1152
1153 an_disable = autoneg == AUTONEG_DISABLE;
1154 an_changes = ((!an_disable && an_disable_admin) ||
1155 (an_disable && !an_disable_admin));
1156
1157 if (!an_changes && link_modes == eproto.admin)
1158 goto out;
1159
1160 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1161 mlx5_toggle_port_link(mdev);
1162
1163 out:
1164 return err;
1165 }
1166
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1167 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1168 const struct ethtool_link_ksettings *link_ksettings)
1169 {
1170 struct mlx5e_priv *priv = netdev_priv(netdev);
1171
1172 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1173 }
1174
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1175 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1176 {
1177 return sizeof(priv->rss_params.toeplitz_hash_key);
1178 }
1179
mlx5e_get_rxfh_key_size(struct net_device * netdev)1180 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1181 {
1182 struct mlx5e_priv *priv = netdev_priv(netdev);
1183
1184 return mlx5e_ethtool_get_rxfh_key_size(priv);
1185 }
1186
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1187 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1188 {
1189 return MLX5E_INDIR_RQT_SIZE;
1190 }
1191
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1192 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1193 {
1194 struct mlx5e_priv *priv = netdev_priv(netdev);
1195
1196 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1197 }
1198
mlx5e_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)1199 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1200 u8 *hfunc)
1201 {
1202 struct mlx5e_priv *priv = netdev_priv(netdev);
1203 struct mlx5e_rss_params *rss = &priv->rss_params;
1204
1205 if (indir)
1206 memcpy(indir, rss->indirection_rqt,
1207 sizeof(rss->indirection_rqt));
1208
1209 if (key)
1210 memcpy(key, rss->toeplitz_hash_key,
1211 sizeof(rss->toeplitz_hash_key));
1212
1213 if (hfunc)
1214 *hfunc = rss->hfunc;
1215
1216 return 0;
1217 }
1218
mlx5e_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1219 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1220 const u8 *key, const u8 hfunc)
1221 {
1222 struct mlx5e_priv *priv = netdev_priv(dev);
1223 struct mlx5e_rss_params *rss = &priv->rss_params;
1224 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1225 bool refresh_tirs = false;
1226 bool refresh_rqt = false;
1227 void *in;
1228
1229 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1230 (hfunc != ETH_RSS_HASH_XOR) &&
1231 (hfunc != ETH_RSS_HASH_TOP))
1232 return -EINVAL;
1233
1234 in = kvzalloc(inlen, GFP_KERNEL);
1235 if (!in)
1236 return -ENOMEM;
1237
1238 mutex_lock(&priv->state_lock);
1239
1240 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1241 rss->hfunc = hfunc;
1242 refresh_rqt = true;
1243 refresh_tirs = true;
1244 }
1245
1246 if (indir) {
1247 memcpy(rss->indirection_rqt, indir,
1248 sizeof(rss->indirection_rqt));
1249 refresh_rqt = true;
1250 }
1251
1252 if (key) {
1253 memcpy(rss->toeplitz_hash_key, key,
1254 sizeof(rss->toeplitz_hash_key));
1255 refresh_tirs = refresh_tirs || rss->hfunc == ETH_RSS_HASH_TOP;
1256 }
1257
1258 if (refresh_rqt && test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1259 struct mlx5e_redirect_rqt_param rrp = {
1260 .is_rss = true,
1261 {
1262 .rss = {
1263 .hfunc = rss->hfunc,
1264 .channels = &priv->channels,
1265 },
1266 },
1267 };
1268 u32 rqtn = priv->indir_rqt.rqtn;
1269
1270 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1271 }
1272
1273 if (refresh_tirs)
1274 mlx5e_modify_tirs_hash(priv, in);
1275
1276 mutex_unlock(&priv->state_lock);
1277
1278 kvfree(in);
1279
1280 return 0;
1281 }
1282
1283 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1284 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1285 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1286 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1287 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1288 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1289 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1290
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1291 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1292 u16 *pfc_prevention_tout)
1293 {
1294 struct mlx5e_priv *priv = netdev_priv(netdev);
1295 struct mlx5_core_dev *mdev = priv->mdev;
1296
1297 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1298 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1299 return -EOPNOTSUPP;
1300
1301 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1302 }
1303
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1304 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1305 u16 pfc_preven)
1306 {
1307 struct mlx5e_priv *priv = netdev_priv(netdev);
1308 struct mlx5_core_dev *mdev = priv->mdev;
1309 u16 critical_tout;
1310 u16 minor;
1311
1312 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1313 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1314 return -EOPNOTSUPP;
1315
1316 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1317 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1318 pfc_preven;
1319
1320 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1321 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1322 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1323 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1324 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1325 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1326 return -EINVAL;
1327 }
1328
1329 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1330 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1331 minor);
1332 }
1333
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1334 static int mlx5e_get_tunable(struct net_device *dev,
1335 const struct ethtool_tunable *tuna,
1336 void *data)
1337 {
1338 int err;
1339
1340 switch (tuna->id) {
1341 case ETHTOOL_PFC_PREVENTION_TOUT:
1342 err = mlx5e_get_pfc_prevention_tout(dev, data);
1343 break;
1344 default:
1345 err = -EINVAL;
1346 break;
1347 }
1348
1349 return err;
1350 }
1351
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1352 static int mlx5e_set_tunable(struct net_device *dev,
1353 const struct ethtool_tunable *tuna,
1354 const void *data)
1355 {
1356 struct mlx5e_priv *priv = netdev_priv(dev);
1357 int err;
1358
1359 mutex_lock(&priv->state_lock);
1360
1361 switch (tuna->id) {
1362 case ETHTOOL_PFC_PREVENTION_TOUT:
1363 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1364 break;
1365 default:
1366 err = -EINVAL;
1367 break;
1368 }
1369
1370 mutex_unlock(&priv->state_lock);
1371 return err;
1372 }
1373
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1374 static void mlx5e_get_pause_stats(struct net_device *netdev,
1375 struct ethtool_pause_stats *pause_stats)
1376 {
1377 struct mlx5e_priv *priv = netdev_priv(netdev);
1378
1379 mlx5e_stats_pause_get(priv, pause_stats);
1380 }
1381
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1382 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1383 struct ethtool_pauseparam *pauseparam)
1384 {
1385 struct mlx5_core_dev *mdev = priv->mdev;
1386 int err;
1387
1388 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1389 &pauseparam->tx_pause);
1390 if (err) {
1391 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1392 __func__, err);
1393 }
1394 }
1395
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1396 static void mlx5e_get_pauseparam(struct net_device *netdev,
1397 struct ethtool_pauseparam *pauseparam)
1398 {
1399 struct mlx5e_priv *priv = netdev_priv(netdev);
1400
1401 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1402 }
1403
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1404 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1405 struct ethtool_pauseparam *pauseparam)
1406 {
1407 struct mlx5_core_dev *mdev = priv->mdev;
1408 int err;
1409
1410 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1411 return -EOPNOTSUPP;
1412
1413 if (pauseparam->autoneg)
1414 return -EINVAL;
1415
1416 err = mlx5_set_port_pause(mdev,
1417 pauseparam->rx_pause ? 1 : 0,
1418 pauseparam->tx_pause ? 1 : 0);
1419 if (err) {
1420 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1421 __func__, err);
1422 }
1423
1424 return err;
1425 }
1426
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1427 static int mlx5e_set_pauseparam(struct net_device *netdev,
1428 struct ethtool_pauseparam *pauseparam)
1429 {
1430 struct mlx5e_priv *priv = netdev_priv(netdev);
1431
1432 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1433 }
1434
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct ethtool_ts_info * info)1435 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1436 struct ethtool_ts_info *info)
1437 {
1438 struct mlx5_core_dev *mdev = priv->mdev;
1439
1440 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1441
1442 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1443 info->phc_index == -1)
1444 return 0;
1445
1446 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1447 SOF_TIMESTAMPING_RX_HARDWARE |
1448 SOF_TIMESTAMPING_RAW_HARDWARE;
1449
1450 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1451 BIT(HWTSTAMP_TX_ON);
1452
1453 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1454 BIT(HWTSTAMP_FILTER_ALL);
1455
1456 return 0;
1457 }
1458
mlx5e_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)1459 static int mlx5e_get_ts_info(struct net_device *dev,
1460 struct ethtool_ts_info *info)
1461 {
1462 struct mlx5e_priv *priv = netdev_priv(dev);
1463
1464 return mlx5e_ethtool_get_ts_info(priv, info);
1465 }
1466
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1467 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1468 {
1469 __u32 ret = 0;
1470
1471 if (MLX5_CAP_GEN(mdev, wol_g))
1472 ret |= WAKE_MAGIC;
1473
1474 if (MLX5_CAP_GEN(mdev, wol_s))
1475 ret |= WAKE_MAGICSECURE;
1476
1477 if (MLX5_CAP_GEN(mdev, wol_a))
1478 ret |= WAKE_ARP;
1479
1480 if (MLX5_CAP_GEN(mdev, wol_b))
1481 ret |= WAKE_BCAST;
1482
1483 if (MLX5_CAP_GEN(mdev, wol_m))
1484 ret |= WAKE_MCAST;
1485
1486 if (MLX5_CAP_GEN(mdev, wol_u))
1487 ret |= WAKE_UCAST;
1488
1489 if (MLX5_CAP_GEN(mdev, wol_p))
1490 ret |= WAKE_PHY;
1491
1492 return ret;
1493 }
1494
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1495 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1496 {
1497 __u32 ret = 0;
1498
1499 if (mode & MLX5_WOL_MAGIC)
1500 ret |= WAKE_MAGIC;
1501
1502 if (mode & MLX5_WOL_SECURED_MAGIC)
1503 ret |= WAKE_MAGICSECURE;
1504
1505 if (mode & MLX5_WOL_ARP)
1506 ret |= WAKE_ARP;
1507
1508 if (mode & MLX5_WOL_BROADCAST)
1509 ret |= WAKE_BCAST;
1510
1511 if (mode & MLX5_WOL_MULTICAST)
1512 ret |= WAKE_MCAST;
1513
1514 if (mode & MLX5_WOL_UNICAST)
1515 ret |= WAKE_UCAST;
1516
1517 if (mode & MLX5_WOL_PHY_ACTIVITY)
1518 ret |= WAKE_PHY;
1519
1520 return ret;
1521 }
1522
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1523 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1524 {
1525 u8 ret = 0;
1526
1527 if (mode & WAKE_MAGIC)
1528 ret |= MLX5_WOL_MAGIC;
1529
1530 if (mode & WAKE_MAGICSECURE)
1531 ret |= MLX5_WOL_SECURED_MAGIC;
1532
1533 if (mode & WAKE_ARP)
1534 ret |= MLX5_WOL_ARP;
1535
1536 if (mode & WAKE_BCAST)
1537 ret |= MLX5_WOL_BROADCAST;
1538
1539 if (mode & WAKE_MCAST)
1540 ret |= MLX5_WOL_MULTICAST;
1541
1542 if (mode & WAKE_UCAST)
1543 ret |= MLX5_WOL_UNICAST;
1544
1545 if (mode & WAKE_PHY)
1546 ret |= MLX5_WOL_PHY_ACTIVITY;
1547
1548 return ret;
1549 }
1550
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1551 static void mlx5e_get_wol(struct net_device *netdev,
1552 struct ethtool_wolinfo *wol)
1553 {
1554 struct mlx5e_priv *priv = netdev_priv(netdev);
1555 struct mlx5_core_dev *mdev = priv->mdev;
1556 u8 mlx5_wol_mode;
1557 int err;
1558
1559 memset(wol, 0, sizeof(*wol));
1560
1561 wol->supported = mlx5e_get_wol_supported(mdev);
1562 if (!wol->supported)
1563 return;
1564
1565 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1566 if (err)
1567 return;
1568
1569 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1570 }
1571
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1572 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1573 {
1574 struct mlx5e_priv *priv = netdev_priv(netdev);
1575 struct mlx5_core_dev *mdev = priv->mdev;
1576 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1577 u32 mlx5_wol_mode;
1578
1579 if (!wol_supported)
1580 return -EOPNOTSUPP;
1581
1582 if (wol->wolopts & ~wol_supported)
1583 return -EINVAL;
1584
1585 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1586
1587 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1588 }
1589
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1590 static int mlx5e_get_fecparam(struct net_device *netdev,
1591 struct ethtool_fecparam *fecparam)
1592 {
1593 struct mlx5e_priv *priv = netdev_priv(netdev);
1594 struct mlx5_core_dev *mdev = priv->mdev;
1595 u16 fec_configured;
1596 u32 fec_active;
1597 int err;
1598
1599 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1600
1601 if (err)
1602 return err;
1603
1604 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1605 sizeof(unsigned long) * BITS_PER_BYTE);
1606
1607 if (!fecparam->active_fec)
1608 return -EOPNOTSUPP;
1609
1610 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1611 sizeof(unsigned long) * BITS_PER_BYTE);
1612
1613 return 0;
1614 }
1615
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1616 static int mlx5e_set_fecparam(struct net_device *netdev,
1617 struct ethtool_fecparam *fecparam)
1618 {
1619 struct mlx5e_priv *priv = netdev_priv(netdev);
1620 struct mlx5_core_dev *mdev = priv->mdev;
1621 unsigned long fec_bitmap;
1622 u16 fec_policy = 0;
1623 int mode;
1624 int err;
1625
1626 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);
1627 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1628 return -EOPNOTSUPP;
1629
1630 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1631 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1632 continue;
1633 fec_policy |= (1 << mode);
1634 break;
1635 }
1636
1637 err = mlx5e_set_fec_mode(mdev, fec_policy);
1638
1639 if (err)
1640 return err;
1641
1642 mlx5_toggle_port_link(mdev);
1643
1644 return 0;
1645 }
1646
mlx5e_get_msglevel(struct net_device * dev)1647 static u32 mlx5e_get_msglevel(struct net_device *dev)
1648 {
1649 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1650 }
1651
mlx5e_set_msglevel(struct net_device * dev,u32 val)1652 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1653 {
1654 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1655 }
1656
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1657 static int mlx5e_set_phys_id(struct net_device *dev,
1658 enum ethtool_phys_id_state state)
1659 {
1660 struct mlx5e_priv *priv = netdev_priv(dev);
1661 struct mlx5_core_dev *mdev = priv->mdev;
1662 u16 beacon_duration;
1663
1664 if (!MLX5_CAP_GEN(mdev, beacon_led))
1665 return -EOPNOTSUPP;
1666
1667 switch (state) {
1668 case ETHTOOL_ID_ACTIVE:
1669 beacon_duration = MLX5_BEACON_DURATION_INF;
1670 break;
1671 case ETHTOOL_ID_INACTIVE:
1672 beacon_duration = MLX5_BEACON_DURATION_OFF;
1673 break;
1674 default:
1675 return -EOPNOTSUPP;
1676 }
1677
1678 return mlx5_set_port_beacon(mdev, beacon_duration);
1679 }
1680
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1681 static int mlx5e_get_module_info(struct net_device *netdev,
1682 struct ethtool_modinfo *modinfo)
1683 {
1684 struct mlx5e_priv *priv = netdev_priv(netdev);
1685 struct mlx5_core_dev *dev = priv->mdev;
1686 int size_read = 0;
1687 u8 data[4] = {0};
1688
1689 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1690 if (size_read < 2)
1691 return -EIO;
1692
1693 /* data[0] = identifier byte */
1694 switch (data[0]) {
1695 case MLX5_MODULE_ID_QSFP:
1696 modinfo->type = ETH_MODULE_SFF_8436;
1697 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1698 break;
1699 case MLX5_MODULE_ID_QSFP_PLUS:
1700 case MLX5_MODULE_ID_QSFP28:
1701 /* data[1] = revision id */
1702 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1703 modinfo->type = ETH_MODULE_SFF_8636;
1704 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1705 } else {
1706 modinfo->type = ETH_MODULE_SFF_8436;
1707 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1708 }
1709 break;
1710 case MLX5_MODULE_ID_SFP:
1711 modinfo->type = ETH_MODULE_SFF_8472;
1712 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1713 break;
1714 default:
1715 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1716 __func__, data[0]);
1717 return -EINVAL;
1718 }
1719
1720 return 0;
1721 }
1722
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1723 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1724 struct ethtool_eeprom *ee,
1725 u8 *data)
1726 {
1727 struct mlx5e_priv *priv = netdev_priv(netdev);
1728 struct mlx5_core_dev *mdev = priv->mdev;
1729 int offset = ee->offset;
1730 int size_read;
1731 int i = 0;
1732
1733 if (!ee->len)
1734 return -EINVAL;
1735
1736 memset(data, 0, ee->len);
1737
1738 while (i < ee->len) {
1739 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1740 data + i);
1741
1742 if (!size_read)
1743 /* Done reading */
1744 return 0;
1745
1746 if (size_read < 0) {
1747 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1748 __func__, size_read);
1749 return 0;
1750 }
1751
1752 i += size_read;
1753 offset += size_read;
1754 }
1755
1756 return 0;
1757 }
1758
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)1759 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1760 struct ethtool_flash *flash)
1761 {
1762 struct mlx5_core_dev *mdev = priv->mdev;
1763 struct net_device *dev = priv->netdev;
1764 const struct firmware *fw;
1765 int err;
1766
1767 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1768 return -EOPNOTSUPP;
1769
1770 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1771 if (err)
1772 return err;
1773
1774 dev_hold(dev);
1775 rtnl_unlock();
1776
1777 err = mlx5_firmware_flash(mdev, fw, NULL);
1778 release_firmware(fw);
1779
1780 rtnl_lock();
1781 dev_put(dev);
1782 return err;
1783 }
1784
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)1785 static int mlx5e_flash_device(struct net_device *dev,
1786 struct ethtool_flash *flash)
1787 {
1788 struct mlx5e_priv *priv = netdev_priv(dev);
1789
1790 return mlx5e_ethtool_flash_device(priv, flash);
1791 }
1792
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)1793 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1794 bool is_rx_cq)
1795 {
1796 struct mlx5e_priv *priv = netdev_priv(netdev);
1797 struct mlx5_core_dev *mdev = priv->mdev;
1798 struct mlx5e_channels new_channels = {};
1799 bool mode_changed;
1800 u8 cq_period_mode, current_cq_period_mode;
1801
1802 cq_period_mode = enable ?
1803 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1804 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1805 current_cq_period_mode = is_rx_cq ?
1806 priv->channels.params.rx_cq_moderation.cq_period_mode :
1807 priv->channels.params.tx_cq_moderation.cq_period_mode;
1808 mode_changed = cq_period_mode != current_cq_period_mode;
1809
1810 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1811 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1812 return -EOPNOTSUPP;
1813
1814 if (!mode_changed)
1815 return 0;
1816
1817 new_channels.params = priv->channels.params;
1818 if (is_rx_cq)
1819 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1820 else
1821 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1822
1823 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1824 priv->channels.params = new_channels.params;
1825 return 0;
1826 }
1827
1828 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1829 }
1830
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)1831 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1832 {
1833 return set_pflag_cqe_based_moder(netdev, enable, false);
1834 }
1835
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)1836 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1837 {
1838 return set_pflag_cqe_based_moder(netdev, enable, true);
1839 }
1840
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val)1841 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1842 {
1843 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1844 struct mlx5e_channels new_channels = {};
1845 int err = 0;
1846
1847 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1848 return new_val ? -EOPNOTSUPP : 0;
1849
1850 if (curr_val == new_val)
1851 return 0;
1852
1853 new_channels.params = priv->channels.params;
1854 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1855
1856 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1857 priv->channels.params = new_channels.params;
1858 return 0;
1859 }
1860
1861 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1862 if (err)
1863 return err;
1864
1865 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1866 MLX5E_GET_PFLAG(&priv->channels.params,
1867 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1868
1869 return 0;
1870 }
1871
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)1872 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1873 bool enable)
1874 {
1875 struct mlx5e_priv *priv = netdev_priv(netdev);
1876 struct mlx5_core_dev *mdev = priv->mdev;
1877 int err;
1878
1879 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1880 return -EOPNOTSUPP;
1881
1882 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1883 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1884 return -EINVAL;
1885 }
1886
1887 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1888 if (err)
1889 return err;
1890
1891 priv->channels.params.rx_cqe_compress_def = enable;
1892
1893 return 0;
1894 }
1895
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)1896 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1897 {
1898 struct mlx5e_priv *priv = netdev_priv(netdev);
1899 struct mlx5_core_dev *mdev = priv->mdev;
1900 struct mlx5e_channels new_channels = {};
1901
1902 if (enable) {
1903 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1904 return -EOPNOTSUPP;
1905 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1906 return -EINVAL;
1907 } else if (priv->channels.params.lro_en) {
1908 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1909 return -EINVAL;
1910 }
1911
1912 new_channels.params = priv->channels.params;
1913
1914 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1915 mlx5e_set_rq_type(mdev, &new_channels.params);
1916
1917 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1918 priv->channels.params = new_channels.params;
1919 return 0;
1920 }
1921
1922 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1923 }
1924
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)1925 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1926 {
1927 struct mlx5e_priv *priv = netdev_priv(netdev);
1928 struct mlx5e_channels *channels = &priv->channels;
1929 struct mlx5e_channel *c;
1930 int i;
1931
1932 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1933 priv->channels.params.xdp_prog)
1934 return 0;
1935
1936 for (i = 0; i < channels->num; i++) {
1937 c = channels->c[i];
1938 if (enable)
1939 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1940 else
1941 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1942 }
1943
1944 return 0;
1945 }
1946
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)1947 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
1948 {
1949 struct mlx5e_priv *priv = netdev_priv(netdev);
1950 struct mlx5_core_dev *mdev = priv->mdev;
1951 struct mlx5e_channels new_channels = {};
1952 int err;
1953
1954 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1955 return -EOPNOTSUPP;
1956
1957 new_channels.params = priv->channels.params;
1958
1959 MLX5E_SET_PFLAG(&new_channels.params, flag, enable);
1960
1961 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1962 priv->channels.params = new_channels.params;
1963 return 0;
1964 }
1965
1966 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1967 return err;
1968 }
1969
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)1970 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1971 {
1972 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1973 }
1974
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)1975 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
1976 {
1977 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
1978 }
1979
1980 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1981 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1982 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1983 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1984 { "rx_striding_rq", set_pflag_rx_striding_rq },
1985 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1986 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1987 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
1988 };
1989
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)1990 static int mlx5e_handle_pflag(struct net_device *netdev,
1991 u32 wanted_flags,
1992 enum mlx5e_priv_flag flag)
1993 {
1994 struct mlx5e_priv *priv = netdev_priv(netdev);
1995 bool enable = !!(wanted_flags & BIT(flag));
1996 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1997 int err;
1998
1999 if (!(changes & BIT(flag)))
2000 return 0;
2001
2002 err = mlx5e_priv_flags[flag].handler(netdev, enable);
2003 if (err) {
2004 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
2005 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
2006 return err;
2007 }
2008
2009 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
2010 return 0;
2011 }
2012
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)2013 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
2014 {
2015 struct mlx5e_priv *priv = netdev_priv(netdev);
2016 enum mlx5e_priv_flag pflag;
2017 int err;
2018
2019 mutex_lock(&priv->state_lock);
2020
2021 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
2022 err = mlx5e_handle_pflag(netdev, pflags, pflag);
2023 if (err)
2024 break;
2025 }
2026
2027 mutex_unlock(&priv->state_lock);
2028
2029 /* Need to fix some features.. */
2030 netdev_update_features(netdev);
2031
2032 return err;
2033 }
2034
mlx5e_get_priv_flags(struct net_device * netdev)2035 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2036 {
2037 struct mlx5e_priv *priv = netdev_priv(netdev);
2038
2039 return priv->channels.params.pflags;
2040 }
2041
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2042 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2043 u32 *rule_locs)
2044 {
2045 struct mlx5e_priv *priv = netdev_priv(dev);
2046
2047 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2048 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2049 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2050 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2051 */
2052 if (info->cmd == ETHTOOL_GRXRINGS) {
2053 info->data = priv->channels.params.num_channels;
2054 return 0;
2055 }
2056
2057 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
2058 }
2059
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2060 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2061 {
2062 return mlx5e_ethtool_set_rxnfc(dev, cmd);
2063 }
2064
2065 const struct ethtool_ops mlx5e_ethtool_ops = {
2066 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2067 ETHTOOL_COALESCE_MAX_FRAMES |
2068 ETHTOOL_COALESCE_USE_ADAPTIVE,
2069 .get_drvinfo = mlx5e_get_drvinfo,
2070 .get_link = ethtool_op_get_link,
2071 .get_strings = mlx5e_get_strings,
2072 .get_sset_count = mlx5e_get_sset_count,
2073 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2074 .get_ringparam = mlx5e_get_ringparam,
2075 .set_ringparam = mlx5e_set_ringparam,
2076 .get_channels = mlx5e_get_channels,
2077 .set_channels = mlx5e_set_channels,
2078 .get_coalesce = mlx5e_get_coalesce,
2079 .set_coalesce = mlx5e_set_coalesce,
2080 .get_link_ksettings = mlx5e_get_link_ksettings,
2081 .set_link_ksettings = mlx5e_set_link_ksettings,
2082 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2083 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2084 .get_rxfh = mlx5e_get_rxfh,
2085 .set_rxfh = mlx5e_set_rxfh,
2086 .get_rxnfc = mlx5e_get_rxnfc,
2087 .set_rxnfc = mlx5e_set_rxnfc,
2088 .get_tunable = mlx5e_get_tunable,
2089 .set_tunable = mlx5e_set_tunable,
2090 .get_pause_stats = mlx5e_get_pause_stats,
2091 .get_pauseparam = mlx5e_get_pauseparam,
2092 .set_pauseparam = mlx5e_set_pauseparam,
2093 .get_ts_info = mlx5e_get_ts_info,
2094 .set_phys_id = mlx5e_set_phys_id,
2095 .get_wol = mlx5e_get_wol,
2096 .set_wol = mlx5e_set_wol,
2097 .get_module_info = mlx5e_get_module_info,
2098 .get_module_eeprom = mlx5e_get_module_eeprom,
2099 .flash_device = mlx5e_flash_device,
2100 .get_priv_flags = mlx5e_get_priv_flags,
2101 .set_priv_flags = mlx5e_set_priv_flags,
2102 .self_test = mlx5e_self_test,
2103 .get_msglevel = mlx5e_get_msglevel,
2104 .set_msglevel = mlx5e_set_msglevel,
2105 .get_fecparam = mlx5e_get_fecparam,
2106 .set_fecparam = mlx5e_set_fecparam,
2107 };
2108