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Searched defs:reg (Results 1 – 25 of 79) sorted by relevance

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/arkcompiler/runtime_core/runtime/arch/
Dasm_support.h54 #define CFI_DEF_CFA(reg, offset) .cfi_def_cfa reg, (offset) argument
58 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
60 #define CFI_REL_OFFSET(reg, offset) .cfi_rel_offset reg, (offset) argument
62 #define CFI_OFFSET(reg, offset) .cfi_offset reg, (offset) argument
68 #define CFI_RESTORE(reg) .cfi_restore reg argument
70 #define CFI_REGISTER(reg, old_reg) .cfi_register reg, old_reg argument
79 #define CFI_DEF_CFA(reg, offset) argument
83 #define CFI_DEF_CFA_REGISTER(reg) argument
85 #define CFI_REL_OFFSET(reg, offset) argument
87 #define CFI_OFFSET(reg, offset) argument
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/arkcompiler/runtime_core/compiler/optimizer/optimizations/regalloc/
Dreg_map.cpp26 for (size_t reg = priority_reg; reg < reg_mask.GetSize(); ++reg) { in SetMask() local
34 for (size_t reg = 0; reg < priority_reg; ++reg) { in SetMask() local
42 for (size_t reg = 0; reg < reg_mask.GetSize(); ++reg) { in SetMask() local
54 for (size_t reg = 0; reg < first_callee_reg; ++reg) { in SetCallerFirstMask() local
61 for (size_t reg = last_callee_reg + 1; reg < reg_mask.GetSize(); ++reg) { in SetCallerFirstMask() local
69 for (size_t reg = first_callee_reg; reg <= last_callee_reg; ++reg) { in SetCallerFirstMask() local
77 for (size_t reg = 0; reg < reg_mask.GetSize(); ++reg) { in SetCallerFirstMask() local
94 bool RegisterMap::IsRegAvailable(Register reg, Arch arch) const in IsRegAvailable()
/arkcompiler/runtime_core/runtime/tests/
Dstack_walker_test.cpp216 int32_t ToCalleeRegister(size_t reg) in ToCalleeRegister()
222 int32_t ToCalleeFpRegister(size_t reg) in ToCalleeFpRegister()
289 … success = walker.IterateVRegsWithInfo([&was_set, &walker](const auto &reg_info, const auto &reg) { in TEST_F()
302 success = walker.IterateVRegsWithInfo([&walker](const auto &reg_info, const auto &reg) { in TEST_F()
313 success = walker.IterateVRegsWithInfo([&walker](const auto &reg_info, const auto &reg) { in TEST_F()
323 success = walker.IterateVRegsWithInfo([](const auto &reg_info, const auto &reg) { in TEST_F()
333 success = walker.IterateVRegsWithInfo([](const auto &reg_info, const auto &reg) { in TEST_F()
343 success = walker.IterateVRegsWithInfo([](const auto &reg_info, const auto &reg) { in TEST_F()
459 … = walker.IterateVRegsWithInfo([&reg_index, &walker, &obj](const auto &reg_info, const auto &reg) { in TestModifyManyVregs()
477 … success = walker.IterateVRegsWithInfo([&reg_index, &obj](const auto &reg_info, const auto &reg) { in TestModifyManyVregs()
Dinterpreter_test.cpp694 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jeq(reg, label); }); in TEST_F()
696 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jeq(reg, label); }); in TEST_F()
698 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jeq(reg, label); }); in TEST_F()
701 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jne(reg, label); }); in TEST_F()
703 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jne(reg, label); }); in TEST_F()
705 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jne(reg, label); }); in TEST_F()
708 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jlt(reg, label); }); in TEST_F()
710 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jlt(reg, label); }); in TEST_F()
712 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jlt(reg, label); }); in TEST_F()
715 … [](BytecodeEmitter *emitter, uint8_t reg, const Label &label) { emitter->Jgt(reg, label); }); in TEST_F()
[all …]
/arkcompiler/runtime_core/compiler/optimizer/code_generator/
Dslow_path.h139 void SetTmpReg(Reg reg) in SetTmpReg()
158 void SetDstReg(Reg reg) in SetDstReg()
163 void SetAddrReg(Reg reg) in SetAddrReg()
194 void SetClassReg(Reg reg) in SetClassReg()
207 void SetMethodReg(Reg reg) in SetMethodReg()
Dregisters_description.h82 virtual bool IsRegUsed(ArenaVector<Reg> vec_reg, Reg reg) in IsRegUsed()
139 for (auto reg : regs) { in GetUsedRegsMask() local
Dencode.h713 virtual void AcquireScratchRegister([[maybe_unused]] compiler::Reg reg) in AcquireScratchRegister()
718 virtual void ReleaseScratchRegister([[maybe_unused]] compiler::Reg reg) in ReleaseScratchRegister()
723 virtual bool IsScratchRegisterReleased([[maybe_unused]] compiler::Reg reg) in IsScratchRegisterReleased()
766 virtual void SetRegister(RegMask *mask, VRegMask *vmask, Reg reg) in SetRegister()
771 virtual void SetRegister(RegMask *mask, VRegMask *vmask, Reg reg, bool val) const in SetRegister()
838 virtual void MakeCall([[maybe_unused]] Reg reg) in MakeCall()
863 …virtual void MakeLoadAotTable([[maybe_unused]] intptr_t offset, [[maybe_unused]] compiler::Reg reg) in MakeLoadAotTable()
881 … EncodeJump([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] compiler::Reg reg, in EncodeJump()
888 … EncodeJump([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] compiler::Reg reg, in EncodeJump()
896 … [[maybe_unused]] compiler::Reg reg, [[maybe_unused]] compiler::Condition c) in EncodeJump()
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/arkcompiler/runtime_core/compiler/tests/aarch64/
Dregister64_test.cpp73 for (auto reg : regs) { in TEST_F() local
85 for (auto reg : regs) { in TEST_F() local
91 ScopedTmpRegRef reg(&encoder); in TEST_F() local
/arkcompiler/runtime_core/compiler/tests/aarch32/
Dregister32_test.cpp76 for (auto reg : regs) { in TEST_F() local
88 for (auto reg : regs) { in TEST_F() local
94 ScopedTmpRegRef reg(&encoder); in TEST_F() local
/arkcompiler/runtime_core/compiler/tests/amd64/
Dregister64_test.cpp76 for (auto reg : regs) { in TEST_F() local
88 for (auto reg : regs) { in TEST_F() local
94 ScopedTmpRegRef reg(&encoder); in TEST_F() local
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/x64/
Dassembler_x64.h181 void EmitRexPrefix(Register reg, Register rm) in EmitRexPrefix()
188 void EmitRexPrefixl(Register reg, Register rm) in EmitRexPrefixl()
197 void EmitRexPrefix(Register reg, Operand rm) in EmitRexPrefix()
204 void EmitRexPrefixl(Register reg, Operand rm) in EmitRexPrefixl()
216 void EmitModrm(int32_t reg, Register rm) in EmitModrm()
221 void EmitModrm(Register reg, Register rm) in EmitModrm()
226 void EmitOperand(Register reg, Operand rm) in EmitOperand()
/arkcompiler/runtime_core/compiler/optimizer/code_generator/target/aarch32/
Dtarget.h119 static inline vixl::aarch32::Register VixlReg(Reg reg) in VixlReg()
133 static inline vixl::aarch32::Register VixlRegU(Reg reg) in VixlRegU()
147 static inline vixl::aarch32::VRegister VixlVReg(Reg reg) in VixlVReg()
322 bool IsCalleeRegister(Reg reg) override in IsCalleeRegister()
334 bool IsZeroReg([[maybe_unused]] Reg reg) const override in IsZeroReg()
615 auto reg = GetMasm()->GetScratchVRegisterList()->GetFirstAvailableSRegister(); in AcquireScratchRegister() local
629 auto reg = GetMasm()->GetScratchRegisterList()->GetFirstAvailableRegister(); in AcquireScratchRegister() local
635 void AcquireScratchRegister(Reg reg) override in AcquireScratchRegister()
649 void ReleaseScratchRegister(Reg reg) override in ReleaseScratchRegister()
661 bool IsScratchRegisterReleased(Reg reg) override in IsScratchRegisterReleased()
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Dregfile.cpp56 bool Aarch32RegisterDescription::IsRegUsed(ArenaVector<Reg> vec_reg, Reg reg) in IsRegUsed()
63 bool Aarch32RegisterDescription::IsTmp(Reg reg) in IsTmp()
/arkcompiler/runtime_core/compiler/optimizer/code_generator/target/amd64/
Dtarget.h239 static inline asmjit::x86::Xmm ArchVReg(Reg reg) in ArchVReg()
445 bool IsCalleeRegister(Reg reg) override in IsCalleeRegister()
457 bool IsZeroReg([[maybe_unused]] Reg reg) const override in IsZeroReg()
541 void AcquireScratchRegister(Reg reg) in AcquireScratchRegister()
552 void ReleaseScratchRegister(Reg reg) in ReleaseScratchRegister()
561 bool IsScratchRegisterReleased(Reg reg) in IsScratchRegisterReleased()
786 void AcquireScratchRegister(Reg reg) override in AcquireScratchRegister()
791 void ReleaseScratchRegister(Reg reg) override in ReleaseScratchRegister()
796 bool IsScratchRegisterReleased(Reg reg) override in IsScratchRegisterReleased()
/arkcompiler/runtime_core/runtime/include/
Dcframe.h175 RegRef &&reg) in GetVRegValue()
187 RegRef &&reg) in GetPackVRegValue()
252 SlotType ReadCalleeSavedRegister(size_t reg, bool is_fp, SlotType **callee_stack) const in ReadCalleeSavedRegister()
267 …void WriteCalleeSavedRegister(size_t reg, SlotType value, bool is_fp, SlotType **callee_stack) con… in WriteCalleeSavedRegister()
/arkcompiler/runtime_core/compiler/optimizer/code_generator/target/aarch64/
Dtarget.h117 static inline vixl::aarch64::Register VixlReg(Reg reg) in VixlReg()
141 static inline vixl::aarch64::Register VixlReg(Reg reg, const uint8_t SIZE) in VixlReg()
159 static inline vixl::aarch64::Register VixlRegU(Reg reg) in VixlRegU()
173 static inline vixl::aarch64::VRegister VixlVReg(Reg reg) in VixlVReg()
183 Reg reg = shift.GetBase(); in VixlShift() local
284 bool IsCalleeRegister(Reg reg) override in IsCalleeRegister()
296 bool IsZeroReg(Reg reg) const override in IsZeroReg()
/arkcompiler/ets_frontend/es2panda/compiler/core/
DregAllocator.cpp130 for (auto *reg : registers) { in AdjustInsRegWhenHasSpill() local
157 for (auto *reg : registers) { in AdjustInsSpill() local
194 VReg *reg = *iter; in AdjustRangeInsSpill() local
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
Dassembler_aarch64.h25 Register(RegisterId reg, RegisterType type = RegisterType::X) : reg_(reg), type_(type) {}; in reg_() argument
79 VectorRegister(VectorRegisterId reg, Scale scale = D) : reg_(reg), scale_(scale) {}; in reg_() argument
164 … : reg_(reg), extend_(Extend::NO_EXTEND), shift_(shift), shiftAmount_(shift_amount), immediate_(0) in reg_() argument
168 … : reg_(reg), extend_(extend), shift_(Shift::NO_SHIFT), shiftAmount_(shiftAmount), immediate_(0) in reg_() argument
/arkcompiler/ets_runtime/test/moduletest/builtins/
Dbuiltinsregexp.js38 var reg = /t(e)(st(\d?))/g; variable
/arkcompiler/runtime_core/compiler/tests/
Dlive_registers_test.cpp50 Register reg {0}; in TEST_F() local
102 Register reg {0}; in TEST_F() local
138 Register reg {0}; in TEST_F() local
165 Register reg {0}; in TEST_F() local
Dreg_alloc_common_test.cpp242 auto reg = input.GetInst()->GetDstReg(); in TEST_F() local
269 auto reg = Target(check_graph->GetArch()).GetParamRegId(1); in TEST_F() local
/arkcompiler/ets_frontend/merge_abc/protos/
DassemblyDebug.proto31 int32 reg = 4; field
/arkcompiler/runtime_core/runtime/tooling/
Ddebugger.cpp308 auto reg = GetThisAddrVRegByPandaFrameDyn(frame); in GetThisVariableByFrame() local
311 auto reg = GetThisAddrVRegByPandaFrame(ret.Value()); in GetThisVariableByFrame() local
328 auto reg = GetVRegByPandaFrameDyn(frame, regNumber); in GetVariable() local
338 auto reg = GetVRegByPandaFrame(ret.Value(), regNumber); in GetVariable() local
358 auto reg = GetVRegByPandaFrameDyn(ret.Value(), regNumber); in SetVariable() local
368 auto reg = GetVRegByPandaFrame(ret.Value(), regNumber); in SetVariable() local
729 interpreter::VRegister &reg = thread->GetCurrentFrame()->GetVReg(inst.GetVReg()); in HandlePropertyAccess() local
777 interpreter::VRegister &reg = thread->GetCurrentFrame()->GetVReg(inst.GetVReg()); in HandlePropertyModify() local
891 static inline uint64_t GetVRegValue(VRegRef reg) in GetVRegValue()
/arkcompiler/ets_frontend/merge_abc/src/
DassemblyInsProto.cpp22 for (const auto &reg : insn.regs) { in Serialize() local
/arkcompiler/runtime_core/bytecode_optimizer/
Dreg_encoder.cpp403 auto reg = inst->GetSrcReg(i); in InsertSpillsForInst() local
421 static void IncTempsIfNeeded(const compiler::Register reg, compiler::Register &num_temps) in IncTempsIfNeeded()
451 auto reg = inst->GetSrcReg(i); in CalculateNumNeededTempsForInst() local

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