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/kernel/linux/linux-5.10/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
42 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
45 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
46 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
57 /* Media-dependent registers. */
58 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
59 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
60 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
61 * Lanes B-D are numbered 134-136. */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atlx/
Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
26 #define SPEED_1000 1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Dan Murphy <dmurphy@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dmv88e1xxx.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define MII_GBCR 9 /* 1000Base-T control register */
19 #define MII_GBSR 10 /* 1000Base-T status register */
21 /* 1000Base-T control register fields */
28 /* 1000Base-T status register fields */
/kernel/linux/linux-5.10/include/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/mii.h: definitions for MII-compatible transceivers
53 return (struct mii_ioctl_data *) &rq->ifr_ifru; in if_mii()
66 * between 100T-full and 100T-half. If your phy does not support
90 * @duplex_lock: Non-zero if duplex is locked at full
196 * MII_CTRL1000 register when in 1000T mode.
216 * MII_CTRL1000 register when in 1000T mode.
237 * bits, when in 1000Base-T mode, to ethtool
257 * bits, when in 1000Base-T mode, to ethtool
275 * bits, when in 1000Base-T mode, to ethtool
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_utils.h37 #define FDO_BUG_URL "https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs"
79 #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV)
86 #define add_overflows_t(T, A, B) \ argument
87 __builtin_add_overflow_p((A), (B), (T)0)
89 #define add_overflows_t(T, A, B) ({ \ argument
92 (T)(a + b) < a; \
105 start__ >= max__ || size__ > max__ - start__; \
117 start__ > max__ || size__ > max__ - start__; \
123 /* Note we don't consider signbits :| */
124 #define overflows_type(x, T) \ argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c50 /*we don't have clk folder yet*/
55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
58 (clk_mgr->regs->reg)
62 #define BASE(seg) BASE_INNER(seg) macro
65 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
93 /* fine-grained, only min and max */ in dcn3_init_single_clock()
103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn3_build_wm_range_table()
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table()
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/kernel/linux/linux-5.10/drivers/memory/
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
96 * facilitate bug detection; even if we didn't boot from ROM.
243 /* Define chip-selects as reserved by default until probe completes */
284 rate /= 1000; in gpmc_get_fclk_period()
291 * gpmc_get_clk_period - get period of selected clock domain in ps
[all …]
/kernel/linux/linux-5.10/drivers/watchdog/
Drti_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * (c) Copyright 2019-2020 Texas Instruments Inc.
25 #define MAX_HEARTBEAT 1000
59 * @base - base io address of WD device
60 * @freq - source clock frequency of WDT
61 * @wdd - hold watchdog device as is in WDT core
64 void __iomem *base; member
75 timer_margin = (u64)wdd->timeout * wdt->freq; in rti_wdt_start()
79 writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD); in rti_wdt_start()
88 wdd->min_hw_heartbeat_ms = 500 * wdd->timeout; in rti_wdt_start()
[all …]
/kernel/linux/linux-5.10/arch/mips/alchemy/common/
Dusb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * area. Au1550 has OHCI on different base address. No need to handle
20 #include <asm/mach-au1x00/au1000.h>
28 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */
32 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgt215.c25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
120 hi--; in gt215_link_train_calc()
125 median[i] = ((hi - lo) >> 1) + lo; in gt215_link_train_calc()
138 train->r_100720 = 0; in gt215_link_train_calc()
143 train->r_100720 |= ((median[i] & 0x0f) << (i << 2)); in gt215_link_train_calc()
146 train->r_1111e0 = 0x02000000 | (bin * 0x101); in gt215_link_train_calc()
147 train->r_111400 = 0x0; in gt215_link_train_calc()
156 struct gt215_ltrain *train = &ram->ltrain; in gt215_link_train()
[all …]
/kernel/linux/linux-5.10/net/ethtool/
Dlinkmodes.c1 // SPDX-License-Identifier: GPL-2.0-only
8 struct ethnl_req_info base; member
12 struct ethnl_reply_data base; member
19 container_of(__reply_base, struct linkmodes_reply_data, base)
31 struct net_device *dev = reply_base->dev; in linkmodes_prepare_data()
34 data->lsettings = &data->ksettings.base; in linkmodes_prepare_data()
40 ret = __ethtool_get_link_ksettings(dev, &data->ksettings); in linkmodes_prepare_data()
46 data->peer_empty = in linkmodes_prepare_data()
47 bitmap_empty(data->ksettings.link_modes.lp_advertising, in linkmodes_prepare_data()
59 const struct ethtool_link_ksettings *ksettings = &data->ksettings; in linkmodes_reply_size()
[all …]
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
11 [NETIF_F_SG_BIT] = "tx-scatter-gather",
12 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
13 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
14 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
16 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
17 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
19 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
20 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
21 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_object_blt.c1 // SPDX-License-Identifier: MIT
29 struct drm_i915_private *i915 = to_i915(obj->base.dev); in __perf_fill_blt()
34 ktime_t t[5]; in __perf_fill_blt() local
45 for (pass = 0; pass < ARRAY_SIZE(t); pass++) { in __perf_fill_blt()
46 struct intel_context *ce = engine->kernel_context; in __perf_fill_blt()
62 t[pass] = ktime_sub(t1, t0); in __perf_fill_blt()
68 sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL); in __perf_fill_blt()
70 engine->name, in __perf_fill_blt()
71 obj->base.size >> 10, in __perf_fill_blt()
72 div64_u64(mul_u32_u32(4 * obj->base.size, in __perf_fill_blt()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
45 struct dss_device *dss = pll->dss; in dss_pll_unregister()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
[all …]
/kernel/linux/linux-5.10/drivers/leds/
Dleds-lm3533.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * leds-lm3533.c -- LM3533 LED driver
5 * Copyright (C) 2011-2012 Texas Instruments
61 return led->id + 2; in lm3533_led_get_ctrlbank_id()
64 static inline u8 lm3533_led_get_lv_reg(struct lm3533_led *led, u8 base) in lm3533_led_get_lv_reg() argument
66 return base + led->id; in lm3533_led_get_lv_reg()
71 return led->id; in lm3533_led_get_pattern()
75 u8 base) in lm3533_led_get_pattern_reg() argument
77 return base + lm3533_led_get_pattern(led) * LM3533_REG_PATTERN_STEP; in lm3533_led_get_pattern_reg()
88 dev_dbg(led->cdev.dev, "%s - %d\n", __func__, enable); in lm3533_led_pattern_enable()
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/kernel/linux/linux-5.10/drivers/ide/
Dqd65xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1996-2001 Linus Torvalds & author (see below)
7 * Version 0.03 Cleaned auto-tune, added probe
20 * Samuel Thibault <samuel.thibault@ens-lyon.org>
40 * I/O ports are 0x30-0x31 (and 0x32-0x33 for qd6580)
41 * or 0xb0-0xb1 (and 0xb2-0xb3 for qd6580)
42 * -- qd6500 is a single IDE interface
43 * -- qd6580 is a dual IDE interface
51 * base: Timer1
54 * base+0x01: Config (R/O)
[all …]
/kernel/linux/linux-5.10/arch/h8300/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2001-2014 Yoshinori Sato <ysato@users.sourceforge.jp>
9 * This file handles the architecture-dependent parts of system setup
27 #include <linux/clk-provider.h>
88 memblock_reserve(__pa(_stext), _end - _stext); in bootmem_init()
131 seq_printf(m, "CPU:\t\t%s\n" in show_cpuinfo()
132 "Clock:\t\t%lu.%1luMHz\n" in show_cpuinfo()
133 "BogoMips:\t%lu.%02lu\n" in show_cpuinfo()
134 "Calibration:\t%lu loops\n", in show_cpuinfo()
136 freq/1000, freq%1000, in show_cpuinfo()
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/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* Loop limit on how long we wait for auto-negotiation to complete */
114 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
115 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
121 /* Link Partner Ability Register (Base Page) */
125 /* 1000BASE-T Control Register */
127 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
128 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
130 /* 1000BASE-T Status Register */
138 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igb/
De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
246 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
258 #define SPEED_1000 1000
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/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/
Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
29 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
30 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
33 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
34 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
40 /* connector doesn't config any color_format, use RGB444 as default */ in komeda_crtc_get_color_config()
52 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
53 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
57 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
60 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
[all …]
/kernel/linux/linux-5.10/drivers/cpufreq/
Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
26 #include "cpufreq-dt.h"
75 #define MIN_VOLT_MV 1000
109 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
110 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
111 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
112 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
132 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, in armada37xx_cpufreq_dvfs_setup() argument
166 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/oki-semi/pch_gbe/
Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
21 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
34 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
41 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
59 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
[all …]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
Darmada-37xx-periph.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * TBG-A-P --| | | | | | ______
12 * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
13 * TBG-A-S --| | | | | | |______|
14 * TBG-B-S --|_____| |_______| |_______|
20 #include <linux/clk-provider.h>
201 .parent_names = (const char *[]){ "TBG-A-P", \
202 "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
211 .parent_names = (const char *[]){ "TBG-A-P", \
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