Home
last modified time | relevance | path

Searched +full:16 +full:bit (Results 1 – 25 of 2419) sorted by relevance

12345678910>>...97

/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_reg.h7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
[all …]
Dsm750_accel.h25 #define DE_SOURCE_WRAP BIT(31)
26 #define DE_SOURCE_X_K1_SHIFT 16
27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16)
28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16)
32 #define DE_DESTINATION_WRAP BIT(31)
33 #define DE_DESTINATION_X_SHIFT 16
34 #define DE_DESTINATION_X_MASK (0x1fff << 16)
38 #define DE_DIMENSION_X_SHIFT 16
39 #define DE_DIMENSION_X_MASK (0x1fff << 16)
43 #define DE_CONTROL_STATUS BIT(31)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/
Dmtk_dpi_regs.h10 #define EN BIT(0)
13 #define RST BIT(0)
16 #define INT_VSYNC_EN BIT(0)
17 #define INT_VDE_EN BIT(1)
18 #define INT_UNDERFLOW_EN BIT(2)
21 #define INT_VSYNC_STA BIT(0)
22 #define INT_VDE_STA BIT(1)
23 #define INT_UNDERFLOW_STA BIT(2)
26 #define BG_ENABLE BIT(0)
27 #define IN_RB_SWAP BIT(1)
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
58 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_dev.h11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
23 #define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
[all …]
Docelot_hsio.h85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
[all …]
Docelot_ana.h11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
38 #define ANA_MACTOPTIONS_SHADOW BIT(0)
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/omap3isp/
Dispreg.h48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
67 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4)
68 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwxgmac2.h28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
34 #define XGMAC_CONFIG_GPSL_SHIFT 16
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
42 #define XGMAC_CONFIG_WD BIT(7)
[all …]
Ddwmac4.h62 #define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
63 #define GMAC_RXQCTRL_MCBCQ_SHIFT 16
64 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
66 #define GMAC_RXQCTRL_TACPQE BIT(21)
72 #define GMAC_PACKET_FILTER_PR BIT(0)
73 #define GMAC_PACKET_FILTER_HMC BIT(2)
74 #define GMAC_PACKET_FILTER_PM BIT(4)
75 #define GMAC_PACKET_FILTER_PCF BIT(7)
76 #define GMAC_PACKET_FILTER_HPF BIT(10)
77 #define GMAC_PACKET_FILTER_VTFE BIT(16)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
[all …]
Dmac.h9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
37 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
Dvc4_regs.h27 ('D' << 16))
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34 # define V3D_IDENT1_NSEM_SHIFT 16
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55 # define V3D_SLCACTL_T0CC_SHIFT 16
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
184 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/vsp1/
Dvsp1_regs.h18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1)
36 #define VI6_WFP_IRQ_ENB_FREE BIT(0)
39 #define VI6_WFP_IRQ_STA_DFE BIT(1)
40 #define VI6_WFP_IRQ_STA_FRE BIT(0)
43 #define VI6_DISP_IRQ_ENB_DSTE BIT(8)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/v3d/
Dv3d_regs.h30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
61 # define V3D_HUB_INT_MMU_PTI BIT(4)
62 # define V3D_HUB_INT_MMU_CAP BIT(3)
63 # define V3D_HUB_INT_MSO BIT(2)
64 # define V3D_HUB_INT_TFUC BIT(1)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dmac.h13 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
35 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
37 #define MT_RXD1_NORMAL_CM BIT(23)
[all …]
/kernel/linux/linux-5.10/drivers/infiniband/hw/ocrdma/
Docrdma_sli.h77 OCRDMA_CMD_QUERY_NSMR = 16,
122 #define OCRDMA_MAX_SGID 16
139 OCRDMA_DB_SQ_SHIFT = 16,
153 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */
154 /* Rearm bit */
155 #define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */
156 /* solicited bit */
157 #define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */
164 #define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */
166 #define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_regs.h46 #define BLK_CTRL_EN BIT(0)
48 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
49 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
50 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
56 #define AD_AEN BIT(0)
57 #define AD_YT BIT(1)
58 #define AD_BS BIT(2)
59 #define AD_WB BIT(3)
60 #define AD_TH BIT(4)
73 #define GCU_CONTROL_SRST BIT(16)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/
Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/fsl-dcu/
Dfsl_dcu_drm_drv.h19 #define DCU_MODE_RASTER_EN BIT(14)
28 #define DCU_BGND_R(x) ((x) << 16)
33 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
34 /*Regisiter value 1/16 of horizontal resolution*/
48 #define DCU_SYN_POL_INV_PXCK BIT(6)
49 #define DCU_SYN_POL_NEG BIT(5)
50 #define DCU_SYN_POL_INV_VS_LOW BIT(1)
51 #define DCU_SYN_POL_INV_HS_LOW BIT(0)
54 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
62 #define DCU_INT_STATUS_VSYNC BIT(0)
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/syscon/
Dimx6q-iomuxc-gpr.h60 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16)
61 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16)
62 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
63 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
64 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16)
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
75 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/ti-vpe/
Dvpe_regs.h26 #define VPE_PID_FUNC_SHIFT 16
51 #define VPE_INT0_LIST0_COMPLETE BIT(0)
52 #define VPE_INT0_LIST0_NOTIFY BIT(1)
53 #define VPE_INT0_LIST1_COMPLETE BIT(2)
54 #define VPE_INT0_LIST1_NOTIFY BIT(3)
55 #define VPE_INT0_LIST2_COMPLETE BIT(4)
56 #define VPE_INT0_LIST2_NOTIFY BIT(5)
57 #define VPE_INT0_LIST3_COMPLETE BIT(6)
58 #define VPE_INT0_LIST3_NOTIFY BIT(7)
59 #define VPE_INT0_LIST4_COMPLETE BIT(8)
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/mscc/
Dmscc_mac.h77 #define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA BIT(0)
78 #define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA BIT(4)
79 #define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST BIT(8)
80 #define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST BIT(12)
81 #define MSCC_MAC_CFG_ENA_CFG_RX_ENA BIT(16)
82 #define MSCC_MAC_CFG_ENA_CFG_TX_ENA BIT(20)
86 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE BIT(16)
87 #define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES BIT(14)
90 #define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG BIT(6)
91 #define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA BIT(4)
[all …]

12345678910>>...97