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/kernel/linux/linux-5.10/tools/testing/selftests/drivers/net/mlxsw/
Ddevlink_trap_control.sh12 # | | 2001:db8:1::1/64 |
15 # | | default via 2001:db8:1::2 |
22 # | 2001:db8:1::2/64 |
34 # | | 2001:db8:2::1/64 |
93 simple_if_init $h1 192.0.2.1/24 2001:db8:1::1/64
96 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
101 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
104 simple_if_fini $h1 192.0.2.1/24 2001:db8:1::1/64
109 simple_if_init $h2 198.51.100.1/24 2001:db8:2::1/64
120 simple_if_fini $h2 198.51.100.1/24 2001:db8:2::1/64
[all …]
/kernel/linux/linux-5.10/lib/
Dglobtest.c10 /* Boot with "glob.verbose=1" to show successful tests, too */
24 /* Can't get string literals into a particular section, so... */ in test()
47 * pointed-to strings to be in a particular section.
49 * Anyway, a test consists of:
50 * 1. Expected glob_match result: '1' or '0'.
54 * The list of tests is terminated with a final '\0' instead of
55 * a glob_match result character.
59 "1" "a\0" "a\0"
60 "0" "a\0" "b\0"
61 "0" "a\0" "aa\0"
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/net/
Dfcnal-test.sh8 # 1. icmp, tcp, udp and netfilter
16 # ns-A | ns-B
23 # ns-A:
24 # eth1: 172.16.1.1/24, 2001:db8:1::1/64
25 # lo: 127.0.0.1/8, ::1/128
26 # 172.16.2.1/32, 2001:db8:2::1/128
27 # red: 127.0.0.1/8, ::1/128
28 # 172.16.3.1/32, 2001:db8:3::1/128
31 # eth1: 172.16.1.2/24, 2001:db8:1::2/64
32 # lo2: 127.0.0.1/8, ::1/128
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/
Duncore-other.json4 "Counter": "0,1,2,3",
6 "PerPkg": "1",
11 "Counter": "0,1,2,3",
15 "PerPkg": "1",
21 "Counter": "0,1,2,3",
25 "PerPkg": "1",
31 "Counter": "0,1,2,3",
35 "PerPkg": "1",
41 "Counter": "0,1,2,3",
45 "PerPkg": "1",
[all …]
Dmemory.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
10 "Offcore": "1",
11 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
17 "Counter": "0,1,2,3",
18 "CounterHTOff": "0,1,2,3",
23 "Offcore": "1",
24 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
30 "Counter": "0,1,2,3",
31 "CounterHTOff": "0,1,2,3",
[all …]
Dcache.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
6 "Deprecated": "1",
11 "Offcore": "1",
12 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
18 "Counter": "0,1,2,3",
19 "CounterHTOff": "0,1,2,3",
20 "Deprecated": "1",
25 "Offcore": "1",
26 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
[all …]
Dother.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
10 "Offcore": "1",
11 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
17 "Counter": "0,1,2,3",
18 "CounterHTOff": "0,1,2,3",
23 "Offcore": "1",
24 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
30 "Counter": "0,1,2,3",
31 "CounterHTOff": "0,1,2,3",
[all …]
Dvirtual-memory.json3 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
8 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
13 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 …"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page…
23 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
24 "Counter": "0,1,2,3",
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/
Duncore-other.json4 "Counter": "0,1,2,3",
6 "PerPkg": "1",
11 "Counter": "0,1,2,3",
15 "PerPkg": "1",
21 "Counter": "0,1,2,3",
25 "PerPkg": "1",
31 "Counter": "0,1,2,3",
35 "PerPkg": "1",
41 "Counter": "0,1,2,3",
45 "PerPkg": "1",
[all …]
Dvirtual-memory.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
17 …licDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G)…
22 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
23 "Counter": "0,1,2,3",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
27 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
32 …"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruct…
[all …]
Dmemory.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
10 "Offcore": "1",
11 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
17 "Counter": "0,1,2,3",
18 "CounterHTOff": "0,1,2,3",
23 "Offcore": "1",
24 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
30 "Counter": "0,1,2,3",
31 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
Dcache.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
10 "Offcore": "1",
11 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
17 "Counter": "0,1,2,3",
18 "CounterHTOff": "0,1,2,3,4,5,6,7",
27 "Counter": "0,1,2,3",
28 "CounterHTOff": "0,1,2,3",
33 "Offcore": "1",
34 …rogrammed only with a specific pair of event select and counter MSR, and with specific event codes…
[all …]
/kernel/linux/linux-5.10/kernel/bpf/
Dtnum.c4 * A tnum tracks knowledge about the bits of a value. Each bit can be either
5 * known (0 or 1), or unknown (x). Arithmetic operations on tnums will
13 /* A completely unknown value */
14 const struct tnum tnum_unknown = { .value = 0, .mask = -1 };
26 /* special case, needed because 1ULL << 64 is undefined */ in tnum_range()
29 /* e.g. if chi = 4, bits = 3, delta = (1<<3) - 1 = 7. in tnum_range()
30 * if chi = 0, bits = 0, delta = (1<<0) - 1 = 0, so we return in tnum_range()
33 delta = (1ULL << bits) - 1; in tnum_range()
37 struct tnum tnum_lshift(struct tnum a, u8 shift) in tnum_lshift() argument
39 return TNUM(a.value << shift, a.mask << shift); in tnum_lshift()
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylake/
Dvirtual-memory.json3 …blicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G)…
5 "Counter": "0,1,2,3",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
13 …sed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
15 "Counter": "0,1,2,3",
19 "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
23 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
25 "Counter": "0,1,2,3",
29 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/drivers/net/mlxsw/spectrum-2/
Dtc_flower.sh4 # This test is for checking the A-TCAM and C-TCAM operation in Spectrum-2.
45 local tracepoint=$1
54 local tracepoint=$1
57 perf record -a -q -e $tracepoint sleep $seconds
63 local tracepoint=$1
71 local tracepoint=$1
76 return 1
83 local tracepoint=$1
87 return 1
94 # When only a single mask is required, the device uses the master
[all …]
/kernel/linux/linux-5.10/arch/powerpc/crypto/
Dmd5-asm.S65 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
67 and rT0,b,c; /* 1: f = b and c */ \
69 andc rT1,d,b; /* 1: f' = ~b and d */ \
71 or rT0,rT0,rT1; /* 1: f = f or f' */ \
72 addi w0,w0,k0l; /* 1: wk = w + k */ \
73 add a,a,rT0; /* 1: a = a + f */ \
74 addis w0,w0,k0h; /* 1: wk = w + k' */ \
76 add a,a,w0; /* 1: a = a + wk */ \
78 rotrwi a,a,p; /* 1: a = a rotl x */ \
79 add d,d,w1; /* 2: a = a + wk */ \
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-ebsa110/
Dio.c12 * we must use a trick to get the required behaviour.
14 * The trick employed here is to use long word stores to odd address -1. The
15 * glue logic picks this up as a "trick" access, and asserts the LSB of the
19 * Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller
20 * wiring was screwed in such a way that it had limited memory space access.
34 u32 ret, a = (u32 __force) addr; in __isamem_convert_addr() local
39 * PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | | in __isamem_convert_addr()
40 * | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 | in __isamem_convert_addr()
42 * CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | | in __isamem_convert_addr()
43 * | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x | in __isamem_convert_addr()
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/goldmontplus/
Dvirtual-memory.json3 "CollectPEBSRecord": "1",
4 …all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.",
6 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
12 "BriefDescription": "Page walk completed due to a demand load to a 4K page"
15 "CollectPEBSRecord": "1",
16 …B levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.",
18 "Counter": "0,1,2,3",
20 "PEBScounters": "0,1,2,3",
24 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page"
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/net/forwarding/
Dtc_flower.sh41 tc filter add dev $h2 ingress protocol ip pref 1 handle 101 flower \
46 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac -A 192.0.2.1 -B 192.0.2.2 \
49 tc_check_packets "dev $h2 ingress" 101 1
50 check_fail $? "Matched on a wrong filter"
52 tc_check_packets "dev $h2 ingress" 102 1
55 tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower
67 tc filter add dev $h2 ingress protocol ip pref 1 handle 101 flower \
72 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac -A 192.0.2.1 -B 192.0.2.2 \
75 tc_check_packets "dev $h2 ingress" 101 1
76 check_fail $? "Matched on a wrong filter"
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/
Dvirtual-memory.json4 …sed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
6 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
11 "BriefDescription": "Page walks completed due to a demand data load to a 4K page."
15 … in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
17 "Counter": "0,1,2,3",
19 "PEBScounters": "0,1,2,3",
22 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page."
26 …t caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB l…
28 "Counter": "0,1,2,3",
[all …]
/kernel/linux/linux-5.10/include/drm/
Ddrm_fixed.h4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
35 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ argument
36 #define dfixed_const_half(A) (u32)(((A) << 12) + 2048) argument
37 #define dfixed_const_666(A) (u32)(((A) << 12) + 2731) argument
38 #define dfixed_const_8(A) (u32)(((A) << 12) + 3277) argument
39 #define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) argument
40 #define dfixed_init(A) { .full = dfixed_const((A)) } argument
41 #define dfixed_init_half(A) { .full = dfixed_const_half((A)) } argument
42 #define dfixed_trunc(A) ((A).full >> 12) argument
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/
Dsoftfloat.c16 * of this code was written as part of a project to build a fixed-point vector
29 * (1) they include prominent notice that the work is derivative, and (2) they
42 #define LIT64( a ) a##LL argument
71 bits64 extractFloat64Frac(float64 a);
72 flag extractFloat64Sign(float64 a);
73 int16 extractFloat64Exp(float64 a);
74 int16 extractFloat32Exp(float32 a);
75 flag extractFloat32Sign(float32 a);
76 bits32 extractFloat32Frac(float32 a);
78 void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr);
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-rgb.rst14 These are all packed-pixel formats, meaning all the data for a pixel lie
33 - :cspan:`7` Byte 1
44 - 1
53 - 1
62 - 1
71 - 1
79 - r\ :sub:`1`
82 - g\ :sub:`1`
84 - b\ :sub:`1`
94 - g\ :sub:`1`
[all …]
/kernel/linux/linux-5.10/arch/sh/include/asm/
Dbitops-grb.h8 volatile unsigned int *a = addr; in set_bit() local
11 a += nr >> 5; in set_bit()
12 mask = 1 << (nr & 0x1f); in set_bit()
16 " mova 1f, r0 \n\t" /* r0 = end point */ in set_bit()
19 " mov.l @%1, %0 \n\t" /* load old value */ in set_bit()
21 " mov.l %0, @%1 \n\t" /* store new value */ in set_bit()
22 "1: mov r1, r15 \n\t" /* LOGOUT */ in set_bit()
24 "+r" (a) in set_bit()
32 volatile unsigned int *a = addr; in clear_bit() local
35 a += nr >> 5; in clear_bit()
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]

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