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/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
53 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
[all …]
/kernel/linux/linux-5.10/arch/sh/lib/
Dudivsi3_i4i.S1 /* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
23 Uses a lookup table for divisors in the range -128 .. +128, and
54 mov.l r4,@-r15
56 mov.l r1,@-r15
67 mov.l r4,@-r15
70 mov.l r5,@-r15
108 mov.l r4,@-r15
110 mov.l r1,@-r15
117 mov.l r1,@-r15
132 mov.l r4,@-r15
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/kernel/linux/linux-5.10/arch/sparc/lib/
DM7memset.S15 * Fast assembler language version of the following C-program for memset
16 * which represents the `standard' for the C-library.
25 * } while (--n != 0);
34 * For less than 32 bytes stores, align the address on 4 byte boundary.
35 * Then store as many 4-byte chunks, followed by trailing bytes.
37 * For sizes greater than 32 bytes, align the address on 8 byte boundary.
38 * if (count >= 64) {
39 * store 8-bytes chunks to align the address on 64 byte boundary
42 * 64-byte cache line to zero which will also clear the
47 * ST_CHUNK cache lines (64 bytes each) before the main
[all …]
DNGmemcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define SAVE_AMOUNT 64
166 .align 64
172 save %sp, -SAVE_AMOUNT, %sp
187 * the destination to a 64-byte boundary which can chew up
188 * to (64 - 1) bytes from the length before we perform the
191 cmp %i2, (2 * 64)
206 /* Align destination on 64-byte boundary. */
207 andcc %o0, (64 - 1), %i4
209 sub %i4, 64, %i4
[all …]
DM7memcpy.S15 * Fast assembler language version of the following C-program for memcpy
16 * which represents the `standard' for the C-library.
26 * } while (--n != 0);
49 * if dst on byte 1
51 * if dst on byte 3
52 * load words, shift 1 byte, store words; branch to finish_up
60 * copy with ldx/stx in 8-way unrolled loop;
61 * copy final 0-63 bytes; exit with dst addr
63 * align dst on 64 byte boundary; for main data movement:
66 * lines from memory. But pre-store first element of each cache line
[all …]
/kernel/linux/linux-5.10/lib/lz4/
Dlz4_compress.c2 * LZ4 - Fast LZ compression algorithm
3 * Copyright (C) 2011 - 2016, Yann Collet.
4 * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php)
26 * - LZ4 homepage : http://www.lz4.org
27 * - LZ4 source repository : https://github.com/lz4/lz4
30 * Sven Schmidt <4sschmid@informatik.uni-hamburg.de>
33 /*-************************************
43 static const int LZ4_64Klimit = ((64 * KB) + (MFLIMIT - 1));
45 /*-******************************
54 >> ((MINMATCH * 8) - (LZ4_HASHLOG + 1))); in LZ4_hash4()
[all …]
Dlz4hc_compress.c2 * LZ4 HC - High Compression Mode of LZ4
3 * Copyright (C) 2011-2015, Yann Collet.
5 * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php)
27 * - LZ4 homepage : http://www.lz4.org
28 * - LZ4 source repository : https://github.com/lz4/lz4
31 * Sven Schmidt <4sschmid@informatik.uni-hamburg.de>
34 /*-************************************
47 #define OPTIMAL_ML (int)((ML_MASK - 1) + MINMATCH)
50 >> ((MINMATCH*8) - LZ4HC_HASH_LOG))
61 static void LZ4HC_init(LZ4HC_CCtx_internal *hc4, const BYTE *start) in LZ4HC_init()
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/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
141 * - 0 = Don't wait
142 * - 1 = Wait for tag switch to complete
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
[all …]
Dcvmx-scratch.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 * Scratch memory is byte addressable - all addresses are byte addresses.
40 * compile without warnings for both 32bit and 64bit.
42 #define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */
47 * @address: byte address to read from
59 * @address: byte address to read from
71 * @address: byte address to read from
81 * Reads a 64 bit value from the processor local scratchpad memory.
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/kernel/linux/linux-5.10/drivers/mtd/spi-nor/
Dwinbond.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
19 * Unfortunately, Winbond has re-used the same JEDEC ID for both in w25q256_post_bfpt_fixups()
25 if (bfpt_header->major == SFDP_JESD216_MAJOR && in w25q256_post_bfpt_fixups()
26 bfpt_header->minor == SFDP_JESD216A_MINOR) in w25q256_post_bfpt_fixups()
27 nor->flags |= SNOR_F_4B_OPCODES; in w25q256_post_bfpt_fixups()
37 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
38 { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
39 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
40 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
[all …]
Dsst.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
12 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
13 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8,
15 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16,
17 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32,
19 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
21 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128,
23 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1,
25 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2,
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/macsec/
Dmacsec_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
22 * will match successfully. The total data is 64 bit, i.e. 16 nibbles
52 /*! The 8 bit value used to compare with extracted value for byte 3. */
54 /*! The 8 bit value used to compare with extracted value for byte 2. */
56 /*! The 8 bit value used to compare with extracted value for byte 1. */
58 /*! The 8 bit value used to compare with extracted value for byte 0. */
62 /*! The 64 bit SCI field in the SecTAG. */
82 /*! 0~63: byte location used extracted by packets comparator, which
83 * can be anything from the first 64 bytes of the MAC packets.
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/
Duncore-other.json10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
46 "ScaleUnit": "64Bytes",
57 "ScaleUnit": "64Bytes",
121 "ScaleUnit": "7.11E-06Bytes",
272 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
277 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
282 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
287 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
292 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
297 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/
Duncore-other.json10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
46 "ScaleUnit": "64Bytes",
57 "ScaleUnit": "64Bytes",
121 "ScaleUnit": "7.11E-06Bytes",
272 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
277 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory st…
282 "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
287 …"PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory s…
292 …"BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory writ…
297 …"PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes iss…
[all …]
/kernel/linux/linux-5.10/arch/x86/boot/
Dheader.S1 /* SPDX-License-Identifier: GPL-2.0 */
12 * BIG FAT NOTE: We're in real mode using 64k segments. Therefore segment
28 BOOTSEG = 0x07C0 /* original address of boot-sector */
45 # "MZ", MS-DOS header
95 .byte 0
115 .word section_table - optional_header # SizeOfOptionalHeader
123 .byte 0x02 # MajorLinkerVersion
124 .byte 0x14 # MinorLinkerVersion
141 # PE specification requires ImageBase to be 64k aligned
179 .long (section_table - .) / 8 # NumberOfRvaAndSizes
[all …]
/kernel/linux/linux-5.10/tools/lib/bpf/
Dbpf_endian.h1 /* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */
6 * Isolate byte #n and put it into byte #m, for __u##b type.
7 * E.g., moving byte #6 (nnnnnnnn) into byte #1 (mmmmmmmm) for __u64:
13 #define ___bpf_mvb(x, b, n, m) ((__u##b)(x) << (b-(n+1)*8) >> (b-8) << (m*8))
26 ___bpf_mvb(x, 64, 0, 7) | \
27 ___bpf_mvb(x, 64, 1, 6) | \
28 ___bpf_mvb(x, 64, 2, 5) | \
29 ___bpf_mvb(x, 64, 3, 4) | \
30 ___bpf_mvb(x, 64, 4, 3) | \
31 ___bpf_mvb(x, 64, 5, 2) | \
[all …]
/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_base.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
39 /** \brief Refer to the width of an integer register in bits(either 32 or 64) */
47 /** \brief Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V */
50 #elif __RISCV_XLEN == 64
69 …rv_csr_t b:1; /*!< bit: 1 Tentatively reserved for Bit-Manipulation…
71 …rv_csr_t d:1; /*!< bit: 3 Double-precision floating-point extension…
73 …rv_csr_t f:1; /*!< bit: 5 Single-precision floating-point extension…
76 rv_csr_t i:1; /*!< bit: 8 RV32I/64I/128I base ISA */
79 … /*!< bit: 11 Tentatively reserved for Decimal Floating-Point extension */
[all …]
/kernel/linux/linux-5.10/Documentation/sparc/oradax/
Ddax-hv-api.txt3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
82 … "ORCL,sun4v-dax-fc" is compatible with the "ORCL,sun4v-dax" interface, and includes additional CCB
[all …]
/kernel/linux/linux-5.10/include/uapi/linux/
Dtypes.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
18 * Below are truly Linux-specific types that should never collide with
40 * aligned_u64 should be used in defining kernel<->userspace ABIs to avoid
41 * common 32/64-bit compat problems.
42 * 64-bit values align to 4-byte boundaries on x86_32 (and possibly other
43 * architectures) and to 8-byte boundaries on 64-bit architectures. The new
44 * aligned_64 type enforces 8-byte alignment so that structs containing
45 * aligned_64 values have the same alignment on 32-bit and 64-bit architectures.
46 * No conversions are necessary between 32-bit user-space and a 64-bit kernel.
/kernel/linux/linux-5.10/arch/x86/include/asm/
Dspecial_insns.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <asm/processor-flags.h>
62 * This could fault if CR4 does not exist. Non-existent CR4 in native_read_cr4()
89 asm volatile(".byte 0x0f,0x01,0xee\n\t" in rdpkru()
103 asm volatile(".byte 0x0f,0x01,0xef\n\t" in wrpkru()
217 alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0", in clflushopt()
218 ".byte 0x66; clflush %P0", in clflushopt()
225 volatile struct { char x[64]; } *p = __p; in clwb()
228 ".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])", in clwb()
229 ".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */ in clwb()
[all …]
/kernel/linux/linux-5.10/arch/x86/lib/
Dcopy_user_64.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
45 * copy_user_generic_unrolled - memory copy with exception handling.
60 jb 20f /* less then 8 bytes, go to byte copy loop */
82 leaq 64(%rsi),%rsi
83 leaq 64(%rdi),%rdi
164 jb 2f /* less than 8 bytes, go to byte copy loop */
203 cmpl $64,%edx
204 jb .L_copy_short_string /* less then 64 bytes, avoid the costly 'rep' */
246 * is counter-intuitive, but needed to prevent the code
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Damdgv_sriovmsg.h2 * Copyright 2018-2019 Advanced Micro Devices, Inc.
29 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
35 * 0 64KB 65KB 66KB
37 * | 64KB | 1KB | 1KB |
84 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
107 /* the total structure size in byte */
130 /* MEC FW position in BYTE from the start of VF visible frame buffer */
132 /* MEC FW size in BYTE */
134 /* UVD FW position in BYTE from the start of VF visible frame buffer */
136 /* UVD FW size in BYTE */
[all …]
/kernel/linux/linux-5.10/arch/m68k/fpsp040/
Dbinstr.S5 | Description: Converts a 64-bit binary integer to bcd.
7 | Input: 64-bit binary integer in d2:d3, desired length (LEN) in
9 | in d0. (This pointer must point to byte 4 of the first
12 | Output: LEN bcd digits representing the 64-bit integer.
15 | The 64-bit binary is assumed to have a decimal point before
21 | A1. Init d7 to 1. D7 is the byte digit counter, and if 1, the
23 | to force the first byte formed to have a 0 in the upper 4 bits.
28 | A3. Multiply the fraction in d2:d3 by 8 using bit-field
35 | A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5
38 | A6. Test d7. If zero, the digit formed is the ms digit. If non-
[all …]
/kernel/linux/linux-5.10/drivers/scsi/csiostor/
Dcsio_hw_t5.c4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
42 * Truncation intentional: we only read the bottom 32-bits of the in csio_t5_set_mem_win()
43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to in csio_t5_set_mem_win()
46 * accesses to our Configuration Space and we need to set up the PCI-E in csio_t5_set_mem_win()
48 * coming across the PCI-E link. in csio_t5_set_mem_win()
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), in csio_t5_set_mem_win()
76 -1, 1 }, in csio_t5_pcie_intr_handler()
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, in csio_t5_pcie_intr_handler()
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Daesni-intel_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Implement AES algorithm in Intel AES-NI instructions.
5 * The white paper of AES-NI instructions can be downloaded from:
6 * http://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf
13 * Added RFC4106 AES-GCM support for 128-bit keys under the AEAD
14 * interface for 64-bit kernels.
30 #include <asm/nospec-branch.h>
33 * The following macros are used to move an (un)aligned 16 byte value to/from
37 * since Nehalem (original Core i7) was released. However, the movaps is a byte
104 #define HashKey_k 16*10 // store XOR of High 64 bits and Low 64
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