Searched +full:cortex +full:- +full:a (Results 1 – 25 of 346) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
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| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 The device tree allows to describe the layout of CPUs in a system through
14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
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| D | scu.txt | 3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
4 with a Snoop Control Unit. The register range is usually 256 (0x100)
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
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| D | arm,vexpress-juno.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
18 The board consist of a motherboard and one or more daughterboards (tiles). The
19 motherboard provides a set of peripherals. Processor and RAM "live" on the
22 The motherboard and each core tile should be described by a separate Device
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| /kernel/liteos_m/ |
| D | README_zh.md | 1 # LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a>
3 - [简介](#section11660541593)
4 - [目录](#section161941989596)
5 - [约束](#section119744591305)
6 - [使用说明](#section3732185231214)
7 - [贡献](#section1371123476307)
8 - [相关仓](#section1371113476307)
10 ## 简介<a name="section11660541593"></a>
12 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录…
14 **图 1** OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>
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| D | README.md | 1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
3 - [Introduction](#section11660541593)
4 - [Directory Structure](#section161941989596)
5 - [Constraints](#section119744591305)
6 - [Usage](#section3732185231214)
7 - [Contribution](#section1371123476307)
8 - [Repositories Involved](#section1371113476307)
10 ## Introduction<a name="section11660541593"></a>
12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe…
13 **Figure1** shows the architecture of the LiteOS-M kernel.
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| /kernel/uniproton/src/include/uapi/hw/armv7-m/ |
| D | prt_exc.h | 2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved.
6 * You may obtain a copy of Mulan PSL v2 at:
9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
10 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
12 * Create: 2009-12-22
109 * Cortex-MX异常具体类型:总线状态寄存器入栈时发生错误。
114 * Cortex-MX异常具体类型:总线状态寄存器出栈时发生错误。
119 * Cortex-MX异常具体类型:总线状态寄存器不精确的数据访问违例。
124 * Cortex-MX异常具体类型:总线状态寄存器精确的数据访问违例。
129 * Cortex-MX异常具体类型:总线状态寄存器取指时的访问违例。
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| /kernel/liteos_m/arch/arm/ |
| D | Kconfig | 4 # ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations
10 32-bit ARM architecture implementations, Except the M-profile.
11 It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc.
27 default "armv7-m" if ARCH_ARM_V7M
28 default "armv8-m" if ARCH_ARM_V8M
48 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
49 …VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support co…
54 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
55 …VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support co…
56 …VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to …
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| /kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
54 * Highest priority of a hardware interrupt.
62 * Lowest priority of a hardware interrupt.
71 * Define the type of a hardware interrupt vector table function.
83 * Count of M-Core system interrupt vector.
89 * Count of M-Core interrupt vector.
106 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
116 * Solution: Pass in a valid non-null hardware interrupt handling function.
146 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
9 In a SMP system, the hierarchy of CPUs is defined through three entities that
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
35 A topology description containing phandles to cpu nodes that are not compliant
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| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 1 Chinese translated version of Documentation/arm64/silicon-errata.rst
4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
37 A 类：无可行补救措施的严重缺陷。
46 情况下，为将 A 类缺陷当作 C 类处理，可能需要用类似的手段。这些手段被
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
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| /kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m7/gcc/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M7 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m4/gcc/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
|
| /kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m7/iar/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M7 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
|
| /kernel/liteos_m/arch/arm/cortex-m4/iar/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/liteos_m/arch/arm/cortex-m3/keil/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
|
| /kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
|
| /kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/ |
| D | los_arch_interrupt.h | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 * Highest priority of a hardware interrupt.
63 * Lowest priority of a hardware interrupt.
72 * Define the type of a hardware interrupt vector table function.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,twd.txt | 3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
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| /kernel/liteos_a/ |
| D | README.md | 1 # LiteOS Cortex-A<a name="EN-US_TOPIC_0000001096612501"></a>
3 - [Introduction](#section11660541593)
4 - [Directory Structure](#section161941989596)
5 - [Constraints](#section119744591305)
6 - [Usage](#section741617511812)
7 - [Preparations](#section1579912573329)
8 - [Source Code Acquisition](#section11443189655)
9 - [Compilation and Building](#section2081013992812)
11 - [Repositories Involved](#section1371113476307)
13 ## Introduction<a name="section11660541593"></a>
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