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Searched +full:cortex +full:- +full:m (Results 1 – 25 of 83) sorted by relevance

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/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved. 83 * Count of M-Core system interrupt vector. 89 * Count of M-Core interrupt vector. 106 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 116 * Solution: Pass in a valid non-null hardware interrupt handling function. 146 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 157 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 178 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 196 * Interrupt Priority-Level Registers. 202 * Interrupt enable register for 0-31. [all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M7 platform is [OS_USER_HWI_MIN,… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M7 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m7/iar/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M7 platform is [OS_USER_HWI_MIN,… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M7 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m4/iar/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m3/keil/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M3 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 84 * Count of M-Core system interrupt vector. 90 * Count of M-Core interrupt vector. 113 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MIN… 123 * Solution: Pass in a valid non-null hardware interrupt handling function. 153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 164 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 203 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/
D	README.md	1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a> 3 - [Introduction](#section11660541593) 4 - [Directory Structure](#section161941989596) 5 - [Constraints](#section119744591305) 6 - [Usage](#section3732185231214) 7 - [Contribution](#section1371123476307) 8 - [Repositories Involved](#section1371113476307) 12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe… 13 Figure1 shows the architecture of the LiteOS-M kernel. 15 Figure 1 Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a> [all …]
D	README_zh.md	1 # LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a> 3 - [简介](#section11660541593) 4 - [目录](#section161941989596) 5 - [约束](#section119744591305) 6 - [使用说明](#section3732185231214) 7 - [贡献](#section1371123476307) 8 - [相关仓](#section1371113476307) 12 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录… 14 图 1 OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a> 15 ![](figures/OpenHarmony-LiteOS-M核内核架构图.png "OpenHarmony-LiteOS-M核内核架构图") [all …]
/kernel/liteos_m/arch/arm/
D	Kconfig	4 # ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations 10 32-bit ARM architecture implementations, Except the M-profile. 11 It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc. 27 default "armv7-m" if ARCH_ARM_V7M 28 default "armv8-m" if ARCH_ARM_V8M 48 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles. 49 …VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support co… 54 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles. 55 …VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support co… 56 …VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to … [all …]
/kernel/uniproton/
D	uniproton.gni	1 # Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved. 8 # EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11 # Create: 2022-09-21 25 " genconfig" + " --header-path $MENUCONFIG_H" + 26 " --file-list kconfig_files.txt" + 27 " --env-list kconfig_env.txt" + " --config-out config.gni" ], 143 "$OSTOPDIR/net/lwip-2.1/include" 147 "$OSTOPDIR/net/lwip-2.1/src/driverif.c", 148 "$OSTOPDIR/net/lwip-2.1/src/netdb.c", 149 "$OSTOPDIR/net/lwip-2.1/src/sockets.c", [all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/stm32/
D	st,mlahb.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 title: STMicroelectronics STM32 ML-AHB interconnect bindings 10 - Fabien Dessenne <fabien.dessenne@st.com> 11 - Arnaud Pouliquen <arnaud.pouliquen@st.com> 14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory 17 using different buses (see [2]): balancing the Cortex-M firmware accesses 23 - $ref: /schemas/simple-bus.yaml# [all …]
/kernel/linux/linux-5.10/arch/arm/mm/
D	proc-v7m.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm/mm/proc-v7m.S 8 * This is the "shell" of the ARMv7-M processor support. 14 #include "proc-macros.S" 31 * - loc - location to jump to for soft reset 104 * This should be able to cover all ARMv7-M cores. 140 ldmia sp, {r0-r3, r12} 144 @ Special-purpose control register 150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 152 teq r8, #0 @ re-evalutae condition [all …]`
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
D	actions.yaml	`1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andreas Färber <afaerber@suse.de> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC. 19 - items: 20 - enum: 21 - allo,sparky # Allo.com Sparky 22 - cubietech,cubieboard6 # Cubietech CubieBoard6 [all …]`
/kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/
D	silicon-errata.txt	1 Chinese translated version of Documentation/arm64/silicon-errata.rst 9 M: Will Deacon <will.deacon@arm.com> 12 --------------------------------------------------------------------- 13 Documentation/arm64/silicon-errata.rst 的中文翻译 26 --------------------------------------------------------------------- 51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”-> 62 +----------------+-----------------+-----------------+-------------------------+ 63 \| ARM \| Cortex-A53 \| #826319 \| ARM64_ERRATUM_826319 \| 64 \| ARM \| Cortex-A53 \| #827319 \| ARM64_ERRATUM_827319 \| 65 \| ARM \| Cortex-A53 \| #824069 \| ARM64_ERRATUM_824069 \| [all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/sprd/
D	sc9863a.dtsi	`1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <dt-bindings/clock/sprd,sc9863a-clk.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #address-cells = <2>; 15 #size-cells = <0>; 17 cpu-map { 48 compatible = "arm,cortex-a55"; 50 enable-method = "psci"; 51 cpu-idle-states = <&CORE_PD>; 56 compatible = "arm,cortex-a55"; [all …]`
/kernel/linux/linux-5.10/arch/arm/boot/dts/
D	bcm4708.dtsi	`5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 20 stdout-path = "serial0:115200n8"; 24 #address-cells = <1>; 25 #size-cells = <0>; 26 enable-method = "brcm,bcm-nsp-smp"; 30 compatible = "arm,cortex-a9"; 31 next-level-cache = <&L2>; 37 compatible = "arm,cortex-a9"; 38 next-level-cache = <&L2>; 39 secondary-boot-reg = <0xffff0400>;`
/kernel/linux/linux-5.10/Documentation/arm/stm32/
D	overview.rst	`6 ------------ 8 The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and 9 Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of 13 ------------- 21 ------ 24 contained in arch/arm/mach-stm32 26 There is a generic board board-dt.c in the mach folder which support 32 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 33 - Ludovic Barre <ludovic.barre@st.com> 34 - Gerald Baeza <gerald.baeza@st.com>`
/kernel/linux/linux-5.10/arch/arm64/kernel/
D	cpu_errata.c	1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <linux/arm-smccc.h> 24 if (!is_midr_in_range(midr, &entry->midr_range)) in is_affected_midr_range() 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) in is_affected_midr_range() 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) in is_affected_midr_range() 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); in is_affected_midr_range_list() 55 return model == entry->midr_range.model; in is_kryo_midr() 102 if (cap->capability == ARM64_WORKAROUND_1542419) in cpu_enable_trap_ctr_access() 146 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ argument 147 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) [all …]

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