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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dmmci.txt11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets : phandle to internal reset line.
20 - vqmmc-supply : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
[all …]
/kernel/linux/linux-5.10/drivers/ata/
Dpata_ali.c2 * pata_ali.c - ALI 15x3 PATA for new ATA layer
8 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
9 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
10 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
22 * otherwise should do atapi DMA (For now for old we do PIO only for
42 MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
54 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
55 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
59 .ident = "Toshiba Satellite S1800-814",
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Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
80 HOST_RESET = (1 << 0), /* reset controller; self-clear */
89 HOST_CAP_PART = (1 << 13), /* Partial state capable */
90 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
92 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
98 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dowl-dma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
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Dsocionext,uniphier-xdmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: "dma-controller.yaml#"
22 const: socionext,uniphier-xdmac
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Drenesas,shdma.txt3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
15 - compatible: should be "renesas,shdma-mux"
16 - #dma-cells: should be <1>, see "dmas" property below
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
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Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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Dmv-xor-v2.txt4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
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Dst_fdma.txt3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
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Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
12 DMA clients connected to the STM32 MDMA controller must use the format
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
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Dqcom_hidma_mgmt.txt3 Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
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/kernel/linux/linux-5.10/arch/xtensa/include/asm/
Ddma.h2 * include/asm-xtensa/dma.h
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
17 * This is only to be defined if we have PC-like DMA.
28 * The maximum virtual address to which DMA transfers
31 * NOTE: This is board (platform) specific, not processor-specific!
33 * NOTE: This assumes DMA transfers can only be performed on
36 * means the maximum possible size of this DMA area is
40 * NOTE: When the entire KSEG area is DMA capable, we subtract
48 #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
51 /* Reserve and release a DMA channel */
/kernel/linux/linux-5.10/include/uapi/linux/
Drio_mport_cdev.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
3 * Copyright (c) 2015-2016, Integrated Device Technology Inc.
11 * License(GPL) Version 2, or the BSD-3 Clause license below:
57 * - memory mapped (MAPPED)
58 * - packet generation from memory (TRANSFER)
83 __u32 cap_sys_size; /* Capable system sizes */
84 __u32 cap_addr_size; /* Capable addressing sizes */
85 __u32 cap_transfer_mode; /* Capable transfer modes */
91 * - incoming port-writes
92 * - incoming doorbells
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/kernel/linux/linux-5.10/Documentation/i2c/
Ddma-considerations.rst2 Linux I2C and DMA
5 Given that I2C is a low-speed bus, over which the majority of messages
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
22 -------
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/kernel/linux/linux-5.10/drivers/xen/
Dgntdev-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2006-2007, D G Murray.
29 /* Device for which DMA memory is allocated. */
64 * If dmabuf_vaddr is not NULL then this mapping is backed by DMA
65 * capable memory.
69 /* Flags used to create this DMA buffer: GNTDEV_DMA_FLAG_XXX. */
/kernel/linux/linux-5.10/drivers/vfio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "VFIO Non-Privileged userspace driver framework"
28 See Documentation/driver-api/vfio.rst for more details.
33 bool "VFIO No-IOMMU support"
37 Only with an IOMMU can userspace access to DMA capable devices be
38 considered secure. VFIO No-IOMMU mode enables IOMMU groups for
39 devices without IOMMU backing for the purpose of re-using the VFIO
40 infrastructure in a non-secure mode. Use of this mode will result
43 this mode since there is no IOMMU to provide DMA translation.
50 source "drivers/vfio/fsl-mc/Kconfig"
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Datmel-usart.txt4 - compatible: Should be one of the following:
5 - "atmel,at91rm9200-usart"
6 - "atmel,at91sam9260-usart"
7 - "microchip,sam9x60-usart"
8 - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"
9 - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
10 - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart"
11 - reg: Should contain registers location and length
12 - interrupts: Should contain interrupt
13 - clock-names: tuple listing input clock names.
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
10 capable of performing IPSec operations on ingress/egress packets.
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dmediatek,mtk-xhci.txt6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
22 - power-domains : a phandle to USB power domain node to control USB's
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-at91.txt4 - compatible : Must be one of:
5 "atmel,at91rm9200-i2c",
6 "atmel,at91sam9261-i2c",
7 "atmel,at91sam9260-i2c",
8 "atmel,at91sam9g20-i2c",
9 "atmel,at91sam9g10-i2c",
10 "atmel,at91sam9x5-i2c",
11 "atmel,sama5d4-i2c",
12 "atmel,sama5d2-i2c",
13 "microchip,sam9x60-i2c".
[all …]
/kernel/linux/linux-5.10/drivers/usb/dwc2/
Dcore.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
61 dev_name(hsotg->dev), ##__VA_ARGS__)
66 dev_name(hsotg->dev), ##__VA_ARGS__)
71 /* dwc2-hsotg declarations */
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/kernel/linux/linux-5.10/drivers/video/fbdev/omap/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
30 Say Y here, if your user-space applications are capable of
36 bool "MIPI DBI-C/DCS compatible LCD support"
40 the Mobile Industry Processor Interface DBI-C/DCS
44 bool "TPS65010 LCD controller on OMAP-H3"
53 bool "Set DMA SDRAM access priority high"
57 (SDRAM) this will speed up graphics DMA operations.
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) argument
166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
233 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
242 /* 4C-4F reserved for more max current */
249 /* 55-57 reserved */
254 /* 60-FB reserved */
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/kernel/linux/linux-5.10/arch/alpha/kernel/
Dpci-noop.c1 // SPDX-License-Identifier: GPL-2.0
3 * linux/arch/alpha/kernel/pci-noop.c
5 * Stub PCI interfaces for Jensen-specific kernels.
16 #include <linux/dma-mapping.h>
42 hose_tail = &hose->next; in alloc_pci_controller()
66 for (hose = hose_head; hose; hose = hose->next) in SYSCALL_DEFINE3()
67 if (hose->index == bus) in SYSCALL_DEFINE3()
70 return -ENODEV; in SYSCALL_DEFINE3()
76 return -ENODEV; in SYSCALL_DEFINE3()
81 return hose->index; in SYSCALL_DEFINE3()
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/kernel/linux/linux-5.10/drivers/rapidio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 bool "DMA Engine support for RapidIO"
43 Say Y here if you want to use DMA Engine frameork for RapidIO data
46 memory and memory on remote target device. You need a DMA controller
47 capable to perform data transfers to/from RapidIO.
68 for RapidIO subsystem. You may select single built-in method or
70 Selecting a built-in method disables use of loadable methods.
72 If unsure, select Basic built-in.
87 provides socket-like interface to allow sharing of single RapidIO
88 messaging mailbox between multiple user-space applications.
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