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/kernel/linux/linux-5.10/Documentation/livepatch/
Dcallbacks.rst42 * Post-patch
48 active), used to clean up post-patch callback
51 * Post-unpatch
61 symmetry: pre-patch callbacks have a post-unpatch counterpart and
62 post-patch callbacks have a pre-unpatch counterpart. An unpatch
90 No post-patch, pre-unpatch, or post-unpatch callbacks will be executed
96 will only occur if their corresponding post-patch callback executed).
100 only the post-unpatch callback will be called.
118 patch the data *after* patching is complete with a post-patch callback,
126 may be possible to implement similar updates via pre/post-patch
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dgm200.c82 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument
92 if (!post) in pmu_load()
109 gm200_devinit_preos(struct nv50_devinit *init, bool post) in gm200_devinit_preos() argument
114 pmu_load(init, 0x01, post, NULL, NULL); in gm200_devinit_preos()
118 gm200_devinit_post(struct nvkm_devinit *base, bool post) in gm200_devinit_post() argument
135 ret = pmu_load(init, 0x04, post, &exec, &args); in gm200_devinit_post()
142 if (post) { in gm200_devinit_post()
150 if (post) { in gm200_devinit_post()
158 if (post) { in gm200_devinit_post()
168 gm200_devinit_preos(init, post); in gm200_devinit_post()
[all …]
Dbase.c62 if (init && init->func->post) in nvkm_devinit_post()
63 ret = init->func->post(init, init->post); in nvkm_devinit_post()
74 init->post = true; in nvkm_devinit_fini()
86 /* Override the post flag during the first call if NvForcePost is set */ in nvkm_devinit_preinit()
88 init->post = init->force_post; in nvkm_devinit_preinit()
Dnv50.c101 * missing, assume it's a secondary gpu which requires post in nv50_devinit_preinit()
103 if (!base->post) { in nv50_devinit_preinit()
106 base->post = true; in nv50_devinit_preinit()
112 if (!base->post) { in nv50_devinit_preinit()
116 base->post = true; in nv50_devinit_preinit()
137 while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { in nv50_devinit_init()
169 .post = nv04_devinit_post,
Dtu102.c69 tu102_devinit_post(struct nvkm_devinit *base, bool post) in tu102_devinit_post() argument
72 gm200_devinit_preos(init, post); in tu102_devinit_post()
79 .post = tu102_devinit_post,
/kernel/linux/linux-5.10/tools/testing/selftests/livepatch/
Dtest-callbacks.sh22 # according to the klp_patch, their post-patch callbacks run and the
26 # unpatching transition starts. klp_objects are reverted, post-patch
67 # - On livepatch enable, only pre/post-patch callbacks are executed for
71 # pre/post-patch callbacks are executed.
74 # $MOD_TARGET) pre/post-unpatch callbacks are executed.
119 # post-unpatch callbacks are executed when this occurs.
121 # - When the livepatch is disabled, pre and post-unpatch callbacks are
166 # pre/post-patch callbacks are executed.
170 # post-unpatch callbacks are executed when this occurs.
213 # - As expected, only pre/post-(un)patch handlers are executed for
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/kernel/linux/linux-5.10/drivers/media/i2c/cx25840/
Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
77 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
78 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
98 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
114 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
115 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
135 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
153 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dclk-alpha-pll.h78 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
81 * @width: width of post-divider
82 * @post_div_shift: shift to differentiate between odd & even post-divider
83 * @post_div_table: table with PLL odd and even post-divider settings
84 * @num_post_div: Number of PLL post-divider settings
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
/kernel/liteos_a/testsuites/kernel/sample/kernel_base/ipc/sem/smp/
DIt_smp_los_sem_030.c100 …(g_ret1 == LOS_OK) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_OK)) { // pend-post-del ///post-pend-del in Testcase()
102 (g_ret3 == LOS_OK)) { // del-pend-post//del-post-pend in Testcase()
103 …(g_ret1 == LOS_OK) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_ERRNO_SEM_PENDED)) { // pend-delete-post in Testcase()
104 … ((g_ret1 == LOS_ERRNO_SEM_INVALID) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_OK)) { // post-del-pend in Testcase()
/kernel/linux/linux-5.10/tools/testing/selftests/drivers/net/netdevsim/
Ddevlink.sh105 check_value max_macs post-set 16 32
106 check_value test1 post-set false Y
110 check_value max_macs post-reload 16 16
111 check_value test1 post-reload false N
150 check_region_snapshot_count dummy post-first-snapshot 1
154 check_region_snapshot_count dummy post-second-snapshot 2
158 check_region_snapshot_count dummy post-third-snapshot 3
163 check_region_snapshot_count dummy post-first-delete 2
168 check_region_snapshot_count dummy post-first-request 3
188 check_region_snapshot_count dummy post-second-delete 2
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/matrox/
Dmatroxfb_misc.h9 unsigned int* in, unsigned int* feed, unsigned int* post);
13 unsigned int *post) in PLL_calcclock() argument
15 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
95 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
96 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18 in set_audclk_freq()
130 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
131 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16 in set_audclk_freq()
167 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
168 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30 in set_audclk_freq()
206 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
207 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24 in set_audclk_freq()
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/tc-testing/creating-plugins/
DAddingPlugins.txt23 post (the post-suite stage)
52 post-suite method using this info passed in to the pre_suite method.
82 'post'
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * BEFORE the pipe-control with a post-sync op and no write-cache
44 * - Post-Sync Operation ([13] of DW1)
49 * Post-sync nonzero is what triggered this second workaround, so we
124 * TLB invalidate requires a post-sync write. in gen6_emit_flush_rcs()
199 * Post-Sync Operation field is a value of 1h or 3h." in mi_flush_dw()
306 * CS_STALL suggests at least a post-sync write. in gen7_emit_flush_rcs()
/kernel/linux/linux-5.10/arch/x86/include/asm/
Dparavirt_types.h492 pre, post, ...) \ argument
502 post \
512 post \
523 #define __PVOP_CALL(rettype, op, pre, post, ...) \ argument
525 EXTRA_CLOBBERS, pre, post, ##__VA_ARGS__)
527 #define __PVOP_CALLEESAVE(rettype, op, pre, post, ...) \ argument
530 pre, post, ##__VA_ARGS__)
533 #define ____PVOP_VCALL(op, clbr, call_clbr, extra_clbr, pre, post, ...) \ argument
539 post \
547 #define __PVOP_VCALL(op, pre, post, ...) \ argument
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/kernel/linux/linux-5.10/sound/core/
Dpcm_timer.c21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
37 post = 1; in snd_pcm_timer_resolution_change()
40 post *= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
/kernel/linux/linux-5.10/drivers/mmc/core/
Dcore.h153 * mmc_post_req - Post process a completed request
154 * @host: MMC host to post process command
155 * @mrq: MMC request to post process for
158 * Let the host post process a completed request. Post processing of
/kernel/linux/linux-5.10/drivers/infiniband/hw/qedr/
Dqedr_roce_cm.c432 DP_ERR(dev, "gsi post send: failed to init header\n"); in qedr_gsi_build_header()
555 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n", in qedr_gsi_post_send()
561 DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n", in qedr_gsi_post_send()
569 "gsi post send: failed due to unsupported opcode %d\n", in qedr_gsi_post_send()
589 "gsi post send: opcode=%d, in_irq=%ld, irqs_disabled=%d, wr_id=%llx\n", in qedr_gsi_post_send()
592 DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc); in qedr_gsi_post_send()
601 "gsi post send: failed second WR. Only one WR may be passed at a time\n"); in qedr_gsi_post_send()
625 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n", in qedr_gsi_post_recv()
635 "gsi post recv: failed to post rx buffer. too many sges %d>%d\n", in qedr_gsi_post_recv()
648 "gsi post recv: failed to post rx buffer (rc=%d)\n", in qedr_gsi_post_recv()
/kernel/linux/linux-5.10/Documentation/ABI/testing/
Dconfigfs-most60 configuration, the creation is post-poned until
115 configuration, the creation is post-poned until
170 configuration, the creation is post-poned until
236 configuration, the creation is post-poned until
/kernel/linux/linux-5.10/drivers/infiniband/hw/i40iw/
Di40iw_uk.c44 * i40iw_nop_1 - insert a nop wqe and move head. no post work
84 * i40iw_qp_post_wr - post wr to hrdware
242 * @info: post sq information
243 * @post_sq: flag to post sq
310 * @info: post sq information
312 * @post_sq: flag to post sq
358 * @info: post sq information
360 * @post_sq: flag to post sq
419 * @info: post sq information
420 * @post_sq: flag to post sq
[all …]
/kernel/linux/linux-5.10/drivers/clk/analogbits/
Dwrpll-cln28hpc.c36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
39 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
72 * on the input clock frequency after the post-R-divider @post_divr_freq.
83 WARN(1, "%s: post-divider reference freq out of range: %lu", in __wrpll_calc_filter_range()
133 * Determine a reasonable value for the PLL Q post-divider, based on the
203 * @target_rate: target PLL output clock rate (post-Q-divider)
320 * post-divider).
/kernel/linux/linux-5.10/drivers/clk/ingenic/
Dcgu.h33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
37 VPP: Video Post Processing
40 The Video Post Processing is in charge of the scaling and blending of the
43 scaler and a "post-blending" to merge with the OSD Planes.
/kernel/linux/linux-5.10/tools/testing/selftests/tc-testing/
DREADME134 -P, --pause Pause execution just before post-suite stage
198 pre- and post-suite
199 pre- and post-case
200 pre- and post-execute stage
220 - post (post-suite)

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