| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | anatop-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Anatop Voltage Regulators
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: "regulator.yaml#"
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
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| /kernel/linux/linux-5.10/drivers/regulator/ |
| D | anatop-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0+
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
92 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
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| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | anatop.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
35 static struct regmap *anatop; variable
37 static void imx_anatop_enable_weak2p5(bool enable) in imx_anatop_enable_weak2p5() argument
41 regmap_read(anatop, ANADIG_ANA_MISC0, &val); in imx_anatop_enable_weak2p5()
45 reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? in imx_anatop_enable_weak2p5()
47 regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); in imx_anatop_enable_weak2p5()
50 static void imx_anatop_enable_fet_odrive(bool enable) in imx_anatop_enable_fet_odrive() argument
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
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| D | mach-imx6q.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
65 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
66 * as they are used for slots1-7 PERST#
75 if (dev->devfn != 0) in ventana_pciesw_early_fixup()
79 dw |= 0xaaa8; // GPIO1-7 outputs in ventana_pciesw_early_fixup()
83 dw |= 0xfe; // GPIO1-7 output high in ventana_pciesw_early_fixup()
96 /* To enable AR8031 output a 125MHz clk from CLK_25M */ in ar8031_phy_fixup()
132 * Enable 125MHz clock from CLK_25M on the AR8031. This in ar8035_phy_fixup()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx6qdl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
54 compatible = "fsl,imx-ckil", "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <32768>;
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| D | imx6sl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a9";
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| D | imx6sx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
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| D | imx6ul.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
55 #address-cells = <1>;
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| D | imx7s.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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| D | imx6sll.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/drivers/usb/phy/ |
| D | phy-mxs-usb.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012-2014 Freescale Semiconductor, Inc.
47 #define BM_USBPHY_CTRL_SFTRST BIT(31)
48 #define BM_USBPHY_CTRL_CLKGATE BIT(30)
49 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
50 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
51 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
52 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
53 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
54 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-imx6sl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
13 #include <dt-bindings/clock/imx6sl-clock.h>
18 #define BM_CCSR_PLL1_SW_CLK_SEL BIT(2)
21 #define BM_CDHIPR_ARM_PODF_BUSY BIT(16)
28 #define BM_PLL_ARM_POWERDOWN BIT(12)
29 #define BM_PLL_ARM_ENABLE BIT(13)
30 #define BM_PLL_ARM_LOCK BIT(31)
122 * 396MHz -> 132MHz;
123 * 792MHz -> 158.4MHz;
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| D | clk-vf610.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012-2013 Freescale Semiconductor, Inc.
10 #include <dt-bindings/clock/vf610-clock.h>
199 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); in vf610_clocks_init()
252 clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); in vf610_clocks_init()
347 * selectable clock sources, both use a common enable bit in vf610_clocks_init()
349 * "ftm0_ext_fix" make it serve only for enable/disable. in vf610_clocks_init()
440 clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); in vf610_clocks_init()
472 CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
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| D | clk-imx6sll.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017-2018 NXP.
7 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <linux/clk-provider.h>
89 clk_hw_data->num = IMX6SLL_CLK_END; in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
101 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop"); in imx6sll_clocks_init()
148 * Bit 20 is the reserved and read-only bit, we do this only for: in imx6sll_clocks_init()
149 * - Do nothing for usbphy clk_enable/disable in imx6sll_clocks_init()
150 * - Keep refcount when do usbphy clk_enable/disable, in that case, in imx6sll_clocks_init()
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| D | clk-imx6sx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
130 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
146 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
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| D | clk-imx6q.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx6qdl-clock.h>
149 return -ENOENT; in ldb_di_sel_by_clock_id()
160 return -ENOENT; in ldb_di_sel_by_clock_id()
172 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
173 "#clock-cells"); in of_assigned_ldb_sels()
175 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
176 "#clock-cells", index, &clkspec); in of_assigned_ldb_sels()
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| D | clk-imx6ul.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
124 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
136 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
166 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
167 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
169 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0034_linux_drivers_usb_vfio_wdt_tty_uio.patch | 7 Change-Id: I1b7e905c318654a235ffe85d3c392289593c1c9d
9 diff --git a/drivers/Kconfig b/drivers/Kconfig
11 --- a/drivers/Kconfig
13 @@ -238,6 +238,8 @@ source "drivers/counter/Kconfig"
22 diff --git a/drivers/Makefile b/drivers/Makefile
24 --- a/drivers/Makefile
26 @@ -192,5 +192,6 @@ obj-$(CONFIG_GNSS) += gnss/
27 obj-$(CONFIG_INTERCONNECT) += interconnect/
28 obj-$(CONFIG_COUNTER) += counter/
29 obj-$(CONFIG_MOST) += most/
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/ |
| D | 0001_linux_arch.patch | 7 Change-Id: I8c7b42f8858212fb4b2d56a871d3f4d5afc73954
9 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
11 --- a/arch/arm64/Kconfig
13 @@ -183,7 +183,6 @@ config ARM64
17 - select HOLES_IN_ZONE
21 @@ -1023,6 +1022,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
31 @@ -1148,7 +1150,7 @@ config XEN
35 - int
40 @@ -1182,15 +1184,6 @@ config UNMAP_KERNEL_AT_EL0
44 -config MITIGATE_SPECTRE_BRANCH_HISTORY
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