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/kernel/linux/linux-5.10/drivers/mtd/nand/
Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 menu "ECC engine support"
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
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Dmtk-nand.txt5 the nand controller interface driver and the ECC engine driver.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
20 - interrupts: Interrupts of NFI.
21 - clocks: NFI required clocks.
22 - clock-names: NFI clocks internal name.
23 - ecc-engine: Required ECC Engine node.
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Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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Dgpmc-nand.txt7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
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Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
18 - ingenic,jz4740-nand
19 - ingenic,jz4725b-nand
20 - ingenic,jz4780-nand
24 - description: Bank number, offset and size of first attached NAND chip
25 - description: Bank number, offset and size of second attached NAND chip
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Dbrcm,brcmnand.txt3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/ingenic/
Dingenic_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
18 * ingenic_ecc_calculate() - calculate ECC for a data buffer
19 * @ecc: ECC device.
20 * @params: ECC parameters.
22 * @ecc_code: output buffer with ECC.
24 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
35 * ingenic_ecc_correct() - detect and correct bit errors
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/kernel/linux/linux-5.10/include/linux/mtd/
Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
74 * These information are usually used by specific sub-layers to select the
86 * enum nand_page_io_req_type - Direction of an I/O request
96 * struct nand_page_io_req - NAND I/O request object
107 * This object is used to pass per-page I/O requests to NAND sub-layers. This
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/kernel/linux/linux-5.10/include/linux/
Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * ccp_present - check if a CCP device is present
28 * Returns zero if a CCP device is present, -ENODEV otherwise.
33 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
38 * ccp_version - get the version of the CCP
45 * ccp_enqueue_cmd - queue an operation for processing by the CCP
54 * result in a return code of -EBUSY.
60 * will be -EINPROGRESS. Any other "err" value during callback is
64 * the return code is -EINPROGRESS or
65 * the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Domap2.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
20 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
182 * omap_prefetch_enable - configures and starts prefetch transfer
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Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
140 * @rb: Ready-busy line
144 * @ecc_conf: Hardware ECC configuration value
145 * @strength: Register value of the ECC strength
148 * @ecc_bits: Exact number of ECC bits per syndrome
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Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
88 /* Command Engine threads state. */
91 /* Command Engine interrupt thread error status. */
93 /* Command Engine interrupt thread error enable. */
95 /* Command Engine interrupt thread complete status. */
115 /* Size of not-last data sector. */
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "NAND ECC Smart Media byte order"
10 Software ECC according to the Smart Media Specification.
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
26 bool "Support software BCH ECC"
32 ECC codes. They are used with NAND devices requiring more than 1 bit
77 This config enables the ELM hardware engine, which can be used to
78 locate and correct errors when using BCH ECC scheme. This offloads
79 the cpu from doing ECC error searching and correction. However some
80 legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine
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Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
29 * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30 * +-------------------------------------------------------------+
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Dplat_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
24 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in plat_nand_attach_chip()
25 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in plat_nand_attach_chip()
26 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in plat_nand_attach_chip()
40 struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); in plat_nand_probe()
48 dev_err(&pdev->dev, "platform_nand_data is missing\n"); in plat_nand_probe()
49 return -EINVAL; in plat_nand_probe()
52 if (pdata->chip.nr_chips < 1) { in plat_nand_probe()
53 dev_err(&pdev->dev, "invalid number of chips specified\n"); in plat_nand_probe()
54 return -EINVAL; in plat_nand_probe()
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Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
71 /* physical DMA address - 32 bit value*/
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Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * socrates_nand_write_buf - write buffer to chip
44 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
51 * socrates_nand_read_buf - read chip data into buffer
65 out_be32(host->io_base, val); in socrates_nand_read_buf()
67 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
73 * socrates_nand_read_byte - read one byte from the chip
84 * Hardware specific access to control-lines
105 out_be32(host->io_base, val); in socrates_nand_cmd_ctrl()
115 if (in_be32(host->io_base) & FPGA_NAND_BUSY) in socrates_nand_device_ready()
[all …]
Dpasemi_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
33 static const char driver_name[] = "pasemi-nand";
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
42 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); in pasemi_read_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
53 memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); in pasemi_write_buf()
63 out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd); in pasemi_hwcontrol()
[all …]
Dr852.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
36 uint8_t reg = readb(dev->mmio + address); in r852_read_reg()
44 writeb(value, dev->mmio + address); in r852_write_reg()
51 uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); in r852_read_reg_dword()
59 writel(cpu_to_le32(value), dev->mmio + address); in r852_write_reg_dword()
73 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) & in r852_dma_test()
76 if (!dev->dma_usable) in r852_dma_test()
81 dev->dma_usable = 0; in r852_dma_test()
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/kernel/linux/linux-5.10/drivers/crypto/ccp/
Dccp-ops.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2019 Advanced Micro Devices, Inc.
11 #include <linux/dma-mapping.h>
19 #include "ccp-dev.h"
56 #define CCP_NEW_JOBID(ccp) ((ccp->vdata->version == CCP_VERSION(3, 0)) ? \
61 return atomic_inc_return(&ccp->current_id) & CCP_JOBID_MASK; in ccp_gen_jobid()
66 if (wa->dma_count) in ccp_sg_free()
67 dma_unmap_sg(wa->dma_dev, wa->dma_sg_head, wa->nents, wa->dma_dir); in ccp_sg_free()
69 wa->dma_count = 0; in ccp_sg_free()
78 wa->sg = sg; in ccp_init_sg_workarea()
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/
Dpmecc.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
32 * The PMECC is an hardware assisted BCH engine, which means part of the
33 * ECC algorithm is left to the software. The hardware/software repartition
37 * sub-section.
41 * to expose the needed lib/bch.c helpers/functions and re-use them here.
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/kernel/linux/linux-5.10/drivers/edac/
DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
68 It should be noticed that keeping both GHES and a hardware-driven
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/kernel/linux/linux-5.10/drivers/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 Some VIA processors come with an integrated crypto engine
21 (so called VIA PadLock ACE, Advanced Cryptography Engine)
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
62 engine for the CryptoAPI AES algorithm.
65 will be called geode-aes.
142 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
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