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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dst,stpmic1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - pascal Paillet <p.paillet@st.com>
24 "#interrupt-cells":
27 interrupt-controller: true
36 const: st,stpmic1-onkey
40 - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
41 - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
43 interrupt-names:
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/kernel/linux/linux-5.10/drivers/reset/
Dreset-ti-syscon.c2 * TI SYSCON regmap reset driver
4 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/reset/ti-syscon.h>
28 * struct ti_syscon_reset_control - reset control structure
29 * @assert_offset: reset assert control register offset from syscon base
30 * @assert_bit: reset assert bit in the reset assert control register
31 * @deassert_offset: reset deassert control register offset from syscon base
32 * @deassert_bit: reset deassert bit in the reset deassert control register
33 * @status_offset: reset status register offset from syscon base
[all …]
Dreset-pistachio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pistachio SoC Reset Controller driver
14 #include <linux/reset-controller.h>
18 #include <dt-bindings/reset/pistachio-resets.h>
59 return -EINVAL; in pistachio_reset_shift()
67 u32 mask; in pistachio_reset_assert() local
74 mask = BIT(shift); in pistachio_reset_assert()
76 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
77 mask, mask); in pistachio_reset_assert()
84 u32 mask; in pistachio_reset_deassert() local
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Dreset-a10sr.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Reset driver for Altera Arria10 MAX5 System Resource Chip
7 * Adapted from reset-socfpga.c
11 #include <linux/mfd/altera-a10sr.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/altr,rst-mgr-a10sr.h>
40 return -EINVAL; in a10sr_reset_shift()
49 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_update() local
52 return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); in a10sr_reset_update()
73 u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); in a10sr_reset_status() local
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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
76 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, in omap4_prminst_rmw_inst_reg_bits() argument
82 v &= ~mask; in omap4_prminst_rmw_inst_reg_bits()
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
93 * @shift: register bit shift corresponding to the reset line to check
97 * -EINVAL upon parameter error.
[all …]
Dprm2xxx_3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
24 * @shift: register bit shift corresponding to the reset line to check
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
41 * @shift: register bit shift corresponding to the reset line to assert
47 * reset line to be asserted / deasserted in order to fully enable the
48 * IP. These modules may have multiple hard-reset lines that reset
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Dprm33xx.c4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
24 #include "prm-regbits-33xx.h"
42 /* Read-modify-write a register in PRM. Caller must lock */
43 static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_prm_rmw_reg_bits() argument
48 v &= ~mask; in am33xx_prm_rmw_reg_bits()
56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
58 * @shift: register bit shift corresponding to the reset line to check
65 * -EINVAL upon parameter error.
80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
81 * @shift: register bit shift corresponding to the reset line to assert
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/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from ivtv-gpio.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
14 #include "cx18-gpio.h"
15 #include "tuner-xc2028.h"
27 * HVR-1600 GPIO pins, courtesy of Hauppauge:
29 * gpio0: zilog ir process reset pin
31 * gpio12: cx24227 reset pin
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/
Dsyscon-reboot.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic SYSCON mapped register reset driver
10 - Sebastian Reichel <sre@kernel.org>
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
16 mask defined in the reboot node. Default will be little endian mode, 32 bit
18 parental dt-node. So the SYSCON reboot node should be represented as a
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/kernel/linux/linux-5.10/drivers/clk/qcom/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reset-controller.h>
12 #include "reset.h"
16 rcdev->ops->assert(rcdev, id); in qcom_reset()
18 rcdev->ops->deassert(rcdev, id); in qcom_reset()
27 u32 mask; in qcom_reset_assert() local
30 map = &rst->reset_map[id]; in qcom_reset_assert()
31 mask = BIT(map->bit); in qcom_reset_assert()
33 return regmap_update_bits(rst->regmap, map->reg, mask, mask); in qcom_reset_assert()
41 u32 mask; in qcom_reset_deassert() local
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/kernel/linux/linux-5.10/include/linux/input/
Dadp5589.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright 2010-2011 Analog Devices Inc.
47 #define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1)
76 #define ADP5585_GPIMAPSIZE_MAX (ADP5585_GPI_PIN_END - ADP5585_GPI_PIN_BASE + 1)
110 /* ADP5589 Mask Bits:
114 * ---------------- BIT ------------------
127 /* ADP5585 Mask Bits:
131 * ---- BIT -- -----------
149 unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */
158 unsigned char reset_cfg; /* Reset config */
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/kernel/linux/linux-5.10/drivers/input/misc/
Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
33 /* Regulator control registers for shutdown/reset */
53 /* Buck TEST2 registers for shutdown/reset */
72 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
108 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
118 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
130 u8 mask, val; in pmic8xxx_pwrkey_shutdown() local
131 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
133 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
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/kernel/linux/linux-5.10/arch/mips/include/asm/sn/sn0/
Dhubni.h8 * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
28 #define NI_PORT_RESET 0x600008 /* Reset the network interface */
70 * NI_STATUS_REV_ID mask and shift definitions
79 #define NSRI_DOWNREASON_MASK (UINT64_CAST 0x1 << 28) /* out of reset. */
102 /* NI_PORT_RESET mask definitions */
104 #define NPR_PORTRESET (UINT64_CAST 1 << 7) /* Send warm reset */
105 #define NPR_LINKRESET (UINT64_CAST 1 << 1) /* Send link reset */
106 #define NPR_LOCALRESET (UINT64_CAST 1) /* Reset entire hub */
108 /* NI_PROTECTION mask and shift definitions */
112 /* NI_GLOBAL_PARMS mask and shift definitions */
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dlantiq,vrx200-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
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/kernel/linux/linux-5.10/drivers/staging/octeon-usb/
Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
140 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk)
142 * The application uses this bit to mask or unmask the interrupt
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dselftest_reset.c1 // SPDX-License-Identifier: MIT
18 intel_engine_mask_t mask, in __igt_reset_stolen() argument
21 struct i915_ggtt *ggtt = &gt->i915->ggtt; in __igt_reset_stolen()
22 const struct resource *dsm = &gt->i915->dsm; in __igt_reset_stolen()
33 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
42 return -ENOMEM; in __igt_reset_stolen()
46 err = -ENOMEM; in __igt_reset_stolen()
51 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
61 if (!(mask & engine->mask)) in __igt_reset_stolen()
82 dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT); in __igt_reset_stolen()
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Dintel_reset.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008-2018 Intel Corporation
44 struct intel_engine_cs *engine = rq->engine; in engine_skip_context()
45 struct intel_context *hung_ctx = rq->context; in engine_skip_context()
50 lockdep_assert_held(&engine->active.lock); in engine_skip_context()
51 list_for_each_entry_continue(rq, &engine->active.requests, sched.link) in engine_skip_context()
52 if (rq->context == hung_ctx) { in engine_skip_context()
53 i915_request_set_error_once(rq, -EIO); in engine_skip_context()
60 struct drm_i915_file_private *file_priv = ctx->file_priv; in client_mark_guilty()
71 prev_hang = xchg(&file_priv->hang_timestamp, jiffies); in client_mark_guilty()
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/kernel/linux/linux-5.10/arch/alpha/oprofile/
Dop_model_ev5.c30 int i, ctl, reset, need_reset; in common_reg_setup() local
36 PCSEL1: 24-39 in common_reg_setup()
37 CBOX1: 40-47 in common_reg_setup()
38 PCSEL2: 48-63 in common_reg_setup()
39 CBOX2: 64-71 in common_reg_setup()
59 /* Convert the event numbers onto mux_select bit mask. */ in common_reg_setup()
65 ctl |= (event - 24) << 4; in common_reg_setup()
67 ctl |= (event - 40) << cbox1_ofs | 15 << 4; in common_reg_setup()
69 ctl |= event - 48; in common_reg_setup()
71 ctl |= (event - 64) << cbox2_ofs | 15; in common_reg_setup()
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/kernel/linux/linux-5.10/arch/powerpc/platforms/52xx/
Dmpc52xx_common.c27 { .compatible = "fsl,mpc5200-xlb", },
28 { .compatible = "mpc5200-xlb", },
32 { .compatible = "fsl,mpc5200-immr", },
33 { .compatible = "fsl,mpc5200b-immr", },
34 { .compatible = "simple-bus", },
73 out_be32(&xlb->master_pri_enable, 0xff); in mpc5200_setup_xlb_arbiter()
74 out_be32(&xlb->master_priority, 0x11111111); in mpc5200_setup_xlb_arbiter()
79 * transaction and re-enable it afterwards ...) in mpc5200_setup_xlb_arbiter()
83 out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS); in mpc5200_setup_xlb_arbiter()
112 { .compatible = "fsl,mpc5200-gpt", },
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/kernel/linux/linux-5.10/drivers/mfd/
Ducb1x00-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mfd/ucb1x00-core.c
11 * to be used on other non-MCP-enabled hardware platforms.
35 * ucb1x00_io_set_dir - set IO direction
54 spin_lock_irqsave(&ucb->io_lock, flags); in ucb1x00_io_set_dir()
55 ucb->io_dir |= out; in ucb1x00_io_set_dir()
56 ucb->io_dir &= ~in; in ucb1x00_io_set_dir()
58 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); in ucb1x00_io_set_dir()
59 spin_unlock_irqrestore(&ucb->io_lock, flags); in ucb1x00_io_set_dir()
63 * ucb1x00_io_write - set or clear IO outputs
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/kernel/linux/linux-5.10/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_device.c7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
33 dev_dbg(&oct->pci_dev->dev, "BIST enabled for soft reset\n"); in lio_cn6xxx_soft_reset()
45 dev_err(&oct->pci_dev->dev, "Soft reset failed\n"); in lio_cn6xxx_soft_reset()
49 dev_dbg(&oct->pci_dev->dev, "Reset completed\n"); in lio_cn6xxx_soft_reset()
59 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_enable_error_reporting()
61 dev_err(&oct->pci_dev->dev, "PCI-E Link error detected: 0x%08x\n", in lio_cn6xxx_enable_error_reporting()
67 dev_dbg(&oct->pci_dev->dev, "Enabling PCI-E error reporting..\n"); in lio_cn6xxx_enable_error_reporting()
68 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, val); in lio_cn6xxx_enable_error_reporting()
78 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_DEVCTL, &val); in lio_cn6xxx_setup_pcie_mps()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]
/kernel/linux/linux-5.10/drivers/soc/ti/
Domap_prm.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/reset-controller.h>
21 #include <linux/platform_data/ti-prm.h>
31 unsigned int usable_modes; /* Mask of hardware supported modes */
32 unsigned long statechange:1; /* Optional low-power state change */
73 u32 mask; member
126 { .rst = -1 },
132 { .rst = -1 },
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/kernel/linux/linux-5.10/drivers/fpga/
Ddfl-afu-error.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/fpga-dfl.h>
20 #include "dfl-afu.h"
30 /* mask or unmask port errors by the error mask register. */
31 static void __afu_port_err_mask(struct device *dev, bool mask) in __afu_port_err_mask() argument
37 writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK); in __afu_port_err_mask()
40 static void afu_port_err_mask(struct device *dev, bool mask) in afu_port_err_mask() argument
44 mutex_lock(&pdata->lock); in afu_port_err_mask()
45 __afu_port_err_mask(dev, mask); in afu_port_err_mask()
46 mutex_unlock(&pdata->lock); in afu_port_err_mask()
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/kernel/linux/linux-5.10/drivers/reset/hisilicon/
Dreset-hi3660.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2016-2017 Linaro Ltd.
4 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
12 #include <linux/reset-controller.h>
27 unsigned int mask = BIT(idx & 0x1f); in hi3660_reset_program_hw() local
30 return regmap_write(rc->map, offset, mask); in hi3660_reset_program_hw()
32 return regmap_write(rc->map, offset + 4, mask); in hi3660_reset_program_hw()
60 .reset = hi3660_reset_dev,
70 offset = reset_spec->args[0]; in hi3660_reset_xlate()
71 bit = reset_spec->args[1]; in hi3660_reset_xlate()
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