Searched +full:mute +full:- +full:till +full:- +full:lock +full:- +full:en (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Popa Stefan <stefan.popa@analog.com>14 https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf15 https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf20 - adi,adf437121 - adi,adf437228 Definition of the external clock (see clock/clock-bindings.txt)31 clock-names:[all …]
1 // SPDX-License-Identifier: GPL-2.073 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */75 /* MOD2 is the programmable, 14-bit auxiliary fractional modulus */162 * Lock for accessing device registers. Some operations require168 struct mutex lock; member187 val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; in adf4371_pll_fract_n_get_rate()188 tmp = (u64)st->fract2 * st->fpfd; in adf4371_pll_fract_n_get_rate()189 do_div(tmp, st->mod2); in adf4371_pll_fract_n_get_rate()193 ref_div_sel = st->rf_div_sel; in adf4371_pll_fract_n_get_rate()247 return -EINVAL; in adf4371_set_freq()[all …]
6 Change-Id: I9825adaa8537a316db8a1831e759a74223b9e4287 ---9 drivers/block/nbd.c | 6 -12 drivers/clk/clk.c | 2 +-13 drivers/clk/rockchip/Kconfig | 42 +-15 drivers/clk/rockchip/clk-cpu.c | 92 +-16 drivers/clk/rockchip/clk-ddr.c | 171 +-17 drivers/clk/rockchip/clk-half-divider.c | 35 +-18 drivers/clk/rockchip/clk-pll.c | 779 ++-19 drivers/clk/rockchip/clk-rk3399.c | 589 +-[all …]
1 diff -Naur a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile2 --- a/arch/arm/boot/Makefile 2022-05-27 17:20:13.781877650 +08003 +++ b/arch/arm/boot/Makefile 2022-05-31 11:56:47.693259679 +08004 @@ -16,6 +16,7 @@12 @@ -24,10 +25,12 @@13 ZRELADDR := $(zreladdr-y)14 PARAMS_PHYS := $(params_phys-y)15 INITRD_PHYS := $(initrd_phys-y)16 +DTB_OBJS ?= $(dtb-y)21 -targets := Image zImage xipImage bootpImage uImage[all …]