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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dnand-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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/kernel/linux/linux-5.10/drivers/mtd/nand/
Decc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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/kernel/linux/linux-5.10/include/linux/mtd/
Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
21 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for Hardware ECC
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Domap2.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
20 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
131 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
145 struct nand_chip nand; member
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "NAND ECC Smart Media byte order"
10 Software ECC according to the Smart Media Specification.
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
26 bool "Support software BCH ECC"
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
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Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
13 * The main visible difference is that NFCv1 only has Hamming ECC
14 * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
21 * or 4) and each chunk will have its own ECC "digest" of 6B at the
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
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Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
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Dsocrates_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
32 * socrates_nand_write_buf - write buffer to chip
33 * @this: NAND chip object
44 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
51 * socrates_nand_read_buf - read chip data into buffer
52 * @this: NAND chip object
65 out_be32(host->io_base, val); in socrates_nand_read_buf()
67 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
73 * socrates_nand_read_byte - read one byte from the chip
84 * Hardware specific access to control-lines
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Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
59 info->group = 0; in nand_pairing_dist3_get_info()
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Dxway_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
14 /* nand registers */
18 #define NAND_WAIT_RD BIT(0) /* NAND flash status output */
19 #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */
24 * nand commands
25 * The pins of the NAND chip are selected based on the address bits of the
26 * "register" read and write. There are no special registers, but an
41 /* we need to tel the ebu which addr we mapped the nand to */
45 /* we need to tell the EBU that we have nand attached and set it up properly */
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Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
14 /* nand interface + ecc
15 byte write/read does one cycle on nand data lines.
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
29 * on NAND flash memory. Driver uses CDMA mode for
88 /* Command Engine threads state. */
91 /* Command Engine interrupt thread error status. */
93 /* Command Engine interrupt thread error enable. */
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Dstm32_fmc2_nand.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
26 /* ECC step size */
35 /* Max requests done for a 8k nand page size */
41 /* Max ECC buffer length */
246 struct stm32_fmc2_nand nand; member
281 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
282 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_nfc_timings_init() local
283 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
287 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
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Dorion_nand.c2 * NAND support for Marvell Orion SoC platforms
22 #include <linux/platform_data/mtd-orion_nand.h>
40 offs = (1 << board->cle); in orion_nand_cmd_ctrl()
42 offs = (1 << board->ale); in orion_nand_cmd_ctrl()
46 if (nc->options & NAND_BUSWIDTH_16) in orion_nand_cmd_ctrl()
49 writeb(cmd, nc->legacy.IO_ADDR_W + offs); in orion_nand_cmd_ctrl()
54 void __iomem *io_base = chip->legacy.IO_ADDR_R; in orion_nand_read_buf()
62 len--; in orion_nand_read_buf()
68 * Since GCC has no proper constraint (PR 43518) in orion_nand_read_buf()
88 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in orion_nand_attach_chip()
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Dau1550nd.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <asm/mach-au1x00/au1000.h>
15 #include <asm/mach-au1x00/au1550nd.h>
32 * au_write_buf - write buffer to chip
33 * @this: NAND chip object
47 writeb(p[i], ctx->base + MEM_STNAND_DATA); in au_write_buf()
53 * au_read_buf - read chip data into buffer
54 * @this: NAND chip object
68 p[i] = readb(ctx->base + MEM_STNAND_DATA); in au_read_buf()
74 * au_write_buf16 - write buffer to chip
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Ddavinci_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
8 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
24 #include <linux/platform_data/mtd-davinci.h>
25 #include <linux/platform_data/mtd-davinci-aemif.h>
28 * This is a device driver for the NAND flash controller found on the
33 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
34 * available on chips like the DM355 and OMAP-L137 and needed with the
35 * more error-prone MLC NAND chips.
37 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
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Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
144 /* NAND OP_CMDs */
163 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
177 /* ECC modes supported by the controller */
193 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
195 /* Returns the NAND register physical address */
196 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
200 ((chip)->reg_read_dma + \
201 ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
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Dr852.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2009 - Maxim Levitsky
31 MODULE_PARM_DESC(debug, "Debug level (0-2)");
36 uint8_t reg = readb(dev->mmio + address); in r852_read_reg()
44 writeb(value, dev->mmio + address); in r852_write_reg()
51 uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); in r852_read_reg_dword()
59 writel(cpu_to_le32(value), dev->mmio + address); in r852_write_reg_dword()
73 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) & in r852_dma_test()
76 if (!dev->dma_usable) in r852_dma_test()
81 dev->dma_usable = 0; in r852_dma_test()
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Ddiskonchip.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * converted to the generic Reed-Solomon library by Thomas Gleixner <tglx@linutronix.de>
16 * Interface to generic NAND code for M-Systems DiskOnChip devices
79 /* This is the ecc value computed by the HW ecc generator upon writing an empty
85 #define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DO…
86 #define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil)
87 #define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k)
115 /* Sector size for HW ECC */
129 * Reed-Solomon library code.
133 * of the generic Reed-Solomon library. tglx
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/ingenic/
Dingenic_ecc.c1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
18 * ingenic_ecc_calculate() - calculate ECC for a data buffer
19 * @ecc: ECC device.
20 * @params: ECC parameters.
22 * @ecc_code: output buffer with ECC.
24 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
35 * ingenic_ecc_correct() - detect and correct bit errors
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Dingenic_nand_drv.c1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
24 #include <linux/jz4780-nemc.h>
28 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
23 /* Resource names for the GPMI NAND driver. */
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/atmel/
Dpmecc.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
29 * Add Nand Flash Controller support for SAMA5 SoC
32 * The PMECC is an hardware assisted BCH engine, which means part of the
33 * ECC algorithm is left to the software. The hardware/software repartition
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