Home
last modified time | relevance | path

Searched +full:opp +full:- (Results 1 – 25 of 350) sorted by relevance

12345678910>>...14

/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra30-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 opp@51000000,800 {
6 opp-microvolt = <800000 800000 1250000>;
9 opp@51000000,850 {
10 opp-microvolt = <850000 850000 1250000>;
13 opp@51000000,912 {
14 opp-microvolt = <912000 912000 1250000>;
17 opp@102000000,800 {
18 opp-microvolt = <800000 800000 1250000>;
21 opp@102000000,850 {
[all …]
Dtegra20-cpu-opp-microvolt.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 opp@216000000,750 {
6 opp-microvolt = <750000 750000 1125000>;
9 opp@216000000,800 {
10 opp-microvolt = <800000 800000 1125000>;
13 opp@312000000,750 {
14 opp-microvolt = <750000 750000 1125000>;
17 opp@312000000,800 {
18 opp-microvolt = <800000 800000 1125000>;
21 opp@456000000,750 {
[all …]
Dtegra30-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp@51000000,800 {
9 clock-latency-ns = <100000>;
10 opp-supported-hw = <0x1F 0x31FE>;
11 opp-hz = /bits/ 64 <51000000>;
14 opp@51000000,850 {
15 clock-latency-ns = <100000>;
16 opp-supported-hw = <0x1F 0x0C01>;
[all …]
Dtegra20-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "operating-points-v2";
6 opp-shared;
8 opp@216000000,750 {
9 clock-latency-ns = <400000>;
10 opp-supported-hw = <0x0F 0x0003>;
11 opp-hz = /bits/ 64 <216000000>;
14 opp@216000000,800 {
15 clock-latency-ns = <400000>;
16 opp-supported-hw = <0x0F 0x0004>;
[all …]
Dexynos5800.dtsi1 // SPDX-License-Identifier: GPL-2.0
20 compatible = "samsung,exynos5800-clock", "syscon";
24 opp-2000000000 {
25 opp-hz = /bits/ 64 <2000000000>;
26 opp-microvolt = <1312500 1312500 1500000>;
27 clock-latency-ns = <140000>;
29 opp-1900000000 {
30 opp-hz = /bits/ 64 <1900000000>;
31 opp-microvolt = <1262500 1262500 1500000>;
32 clock-latency-ns = <140000>;
[all …]
Drk3229.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /delete-node/ opp-table0;
14 compatible = "operating-points-v2";
15 opp-shared;
17 opp-408000000 {
18 opp-hz = /bits/ 64 <408000000>;
19 opp-microvolt = <950000>;
20 clock-latency-ns = <40000>;
21 opp-suspend;
23 opp-600000000 {
[all …]
Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/opp/
Dqcom-nvmem-cpufreq.txt1 Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
5 the CPU frequencies subset and voltage value of each OPP varies based on
8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
11 to provide the OPP framework with required information (existing HW bitmap).
12 This is used to determine the voltage and frequency value for each OPP of
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
[all …]
Dopp.txt1 Generic OPP (Operating Performance Points) Bindings
2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
10 This document contain multiple versions of OPP binding and only one of them
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
27 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
Dallwinner,sun50i-h6-operating-points.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 OPP varies based on the silicon variant in use. Allwinner Process
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-a311d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-100000000 {
15 opp-hz = /bits/ 64 <100000000>;
16 opp-microvolt = <731000>;
19 opp-250000000 {
20 opp-hz = /bits/ 64 <250000000>;
[all …]
Dmeson-g12b-s922x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12b.dtsi"
10 cpu_opp_table_0: opp-table-0 {
11 compatible = "operating-points-v2";
12 opp-shared;
14 opp-100000000 {
15 opp-hz = /bits/ 64 <100000000>;
16 opp-microvolt = <731000>;
19 opp-250000000 {
20 opp-hz = /bits/ 64 <250000000>;
[all …]
Dmeson-g12a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-op1-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <825000>;
[all …]
Drk3399-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
7 cluster0_opp: opp-table0 {
8 compatible = "operating-points-v2";
9 opp-shared;
12 opp-hz = /bits/ 64 <408000000>;
13 opp-microvolt = <800000>;
14 clock-latency-ns = <40000>;
17 opp-hz = /bits/ 64 <600000000>;
18 opp-microvolt = <800000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
30 operating-points-v2 = <&bus_gscl_opp_table>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 cpu_opp_table: opp-table-cpu {
7 compatible = "allwinner,sun50i-h6-operating-points";
8 nvmem-cells = <&cpu_speed_grade>;
9 opp-shared;
11 opp@480000000 {
12 clock-latency-ns = <244144>; /* 8 32k periods */
13 opp-hz = /bits/ 64 <480000000>;
15 opp-microvolt-speed0 = <880000 880000 1200000>;
16 opp-microvolt-speed1 = <820000 820000 1200000>;
[all …]
Dsun50i-h5-cpu-opp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
5 cpu_opp_table: opp-table-cpu {
6 compatible = "operating-points-v2";
7 opp-shared;
9 opp-408000000 {
10 opp-hz = /bits/ 64 <408000000>;
11 opp-microvolt = <1000000 1000000 1310000>;
12 clock-latency-ns = <244144>; /* 8 32k periods */
15 opp-648000000 {
[all …]
Dsun50i-a64-cpu-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 cpu0_opp_table: opp-table-cpu {
8 compatible = "operating-points-v2";
9 opp-shared;
11 opp-648000000 {
12 opp-hz = /bits/ 64 <648000000>;
13 opp-microvolt = <1040000>;
14 clock-latency-ns = <244144>; /* 8 32k periods */
17 opp-816000000 {
18 opp-hz = /bits/ 64 <816000000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
25 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
[all …]
Dti-cpufreq.txt1 TI CPUFreq and OPP bindings
6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
7 provide the OPP framework with supported hardware information. This is
8 used to determine which OPPs from the operating-points-v2 table get enabled
9 when it is parsed by the OPP framework.
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
[all …]
/kernel/linux/linux-5.10/Documentation/power/
Dopp.rst2 Operating Performance Points (OPP) Library
5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
10 2. Initial OPP List Registration
11 3. OPP Search Functions
12 4. OPP Availability Control Functions
13 5. OPP Data Retrieval Functions
19 1.1 What is an Operating Performance Point (OPP)?
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
[all …]
/kernel/linux/linux-5.10/arch/powerpc/kvm/
Dmpic.c63 #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
116 struct kvm_vcpu *vcpu = current->thread.kvm_vcpu; in get_current_cpu()
117 return vcpu ? vcpu->arch.irq_cpu_id : -1; in get_current_cpu()
120 return -1; in get_current_cpu()
128 static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
133 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
154 bool level:1; /* level-triggered */
171 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) argument
184 /* Count of IRQ sources asserting on non-INT outputs */
241 static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst, in mpic_irq_raise() argument
[all …]
/kernel/linux/linux-5.10/drivers/opp/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP Interface
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated.
22 #include "opp.h"
25 * The root of the list of all opp-tables. All opp_table structures branch off
30 /* Lock to allow exclusive modification to the device and opp lists */
38 list_for_each_entry(opp_dev, &opp_table->dev_list, node) in _find_opp_dev()
39 if (opp_dev->dev == dev) in _find_opp_dev()
51 mutex_lock(&opp_table->lock); in _find_opp_table_unlocked()
53 mutex_unlock(&opp_table->lock); in _find_opp_table_unlocked()
[all …]
Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic OPP debugfs interface
5 * Copyright (C) 2015-2016 Viresh Kumar <viresh.kumar@linaro.org>
17 #include "opp.h"
23 if (dev->parent) in opp_set_dev_name()
24 snprintf(name, NAME_MAX, "%s-%s", dev_name(dev->parent), in opp_set_dev_name()
30 void opp_debug_remove_one(struct dev_pm_opp *opp) in opp_debug_remove_one() argument
32 debugfs_remove_recursive(opp->dentry); in opp_debug_remove_one()
38 struct icc_path *path = fp->private_data; in bw_name_read()
53 static void opp_debug_create_bw(struct dev_pm_opp *opp, in opp_debug_create_bw() argument
[all …]

12345678910>>...14