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Searched +full:phy +full:- +full:dll +full:- +full:delay +full:- +full:sdclk (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
11 - Piotr Sroka <piotrs@cadence.com>
14 - $ref: mmc-controller.yaml
19 - enum:
20 - socionext,uniphier-sd4hc
21 - const: cdns,sd4hc
32 # PHY DLL input delays:
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/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PHY support for Xenon SDHC
8 * Date: 2016-8-24
12 #include <linux/delay.h>
16 #include "sdhci-pltfm.h"
17 #include "sdhci-xenon.h"
19 /* Register base for eMMC PHY 5.0 Version */
21 /* Register base for eMMC PHY 5.1 Version */
113 * List offset of PHY registers and some special register values
114 * in eMMC PHY 5.0 or eMMC PHY 5.1
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Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include "sdhci-pltfm.h"
18 /* HRS - Host Register Set (specific to Cadence) */
19 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
38 /* SRS - Slot Register Set (SDHCI-compatible) */
41 /* PHY */
56 * The tuned val register is 6 bit-wide, but not the whole of the range is
57 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
80 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
81 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
12 compatible = "socionext,uniphier-ld11";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
21 cpu-map {
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Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
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Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/
D0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch7 Change-Id: Iec160bd007994d82f416debdccfbc0d9bdb40470
9 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
11 --- a/drivers/misc/Kconfig
13 @@ -314,6 +314,26 @@ config ISL29020
40 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
42 --- a/drivers/misc/Makefile
44 @@ -19,6 +19,8 @@ obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
45 obj-$(CONFIG_PHANTOM) += phantom.o
46 obj-$(CONFIG_QCOM_COINCELL) += qcom-coincell.o
47 obj-$(CONFIG_QCOM_FASTRPC) += fastrpc.o
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/kernel/linux/patches/linux-4.19/hispark_taurus_patch/
Dhispark_taurus.patch1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -330,7 +330,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -751,6 +751,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
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