| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/backlight/ |
| D | pwm-backlight.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/pwm-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: pwm-backlight bindings
10 - Lee Jones <lee.jones@linaro.org>
11 - Daniel Thompson <daniel.thompson@linaro.org>
12 - Jingoo Han <jingoohan1@gmail.com>
16 const: pwm-backlight
21 pwm-names: true
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| /kernel/liteos_a/testsuites/kernel/sample/kernel_base/ipc/mux/smp/ |
| D | It_smp_los_mux_2018.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
57 dprintf("task f01 post mux\n"); in TaskF01()
78 dprintf("task f02 post mux\n"); in TaskF02()
120 TestBusyTaskDelay(2); // 2, delay for Timing control. in Testcase()
122 ret = OS_TCB_FROM_TID(g_testTaskID01)->taskStatus; in Testcase()
125 ret = OS_TCB_FROM_TID(g_testTaskID02)->taskStatus; in Testcase()
131 LOS_TaskDelay(10); // 10, delay for Timing control. in Testcase()
135 ret = OS_TCB_FROM_TID(g_testTaskID01)->taskStatus; in Testcase()
144 g_flag1 = 0; // mux post in task f01 in Testcase()
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| D | It_smp_los_mux_2015.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
68 PRINT_DEBUG("delay in task f02\n"); in TaskF02()
69 LOS_TaskDelay(10); // 10, delay for Timing control. in TaskF02()
72 PRINT_DEBUG("post mux in task f02\n"); in TaskF02()
81 PRINT_DEBUG("after post in hwi \n"); in HwiF01()
118 TEST_TASK_PARAM_INIT_AFFI(testTask, "it_MUX_2015_task2", TaskF02, TASK_PRIO_TEST_TASK - 1, in Testcase()
141 PRINT_DEBUG("delay in testtask begin\n"); in Testcase()
142 LOS_TaskDelay(20); // 20, delay for Timing control. in Testcase()
143 PRINT_DEBUG("delay in testtask end\n"); in Testcase()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/ |
| D | hid-over-i2c.txt | 1 * HID over I2C Device-Tree bindings
8 http://msdn.microsoft.com/en-us/library/windows/hardware/hh852380.aspx
10 If this binding is used, the kernel module i2c-hid will handle the communication
14 - compatible: must be "hid-over-i2c"
15 - reg: i2c slave address
16 - hid-descr-addr: HID descriptor address
17 - interrupts: interrupt line
23 device-specific compatible properties, which should be used in addition to the
24 "hid-over-i2c" string.
26 - compatible:
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| /kernel/linux/linux-5.10/drivers/mmc/core/ |
| D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <linux/delay.h>
75 void _mmc_detect_change(struct mmc_host *host, unsigned long delay,
123 * mmc_claim_host - exclusively claim a host
138 * mmc_pre_req - Prepare for a new request
148 if (host->ops->pre_req) in mmc_pre_req()
149 host->ops->pre_req(host, mrq); in mmc_pre_req()
153 * mmc_post_req - Post process a completed request
154 * @host: MMC host to post process command
155 * @mrq: MMC request to post process for
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| /kernel/liteos_a/testsuites/kernel/sample/kernel_base/ipc/sem/smp/ |
| D | It_smp_los_sem_030.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
50 for (i = 0; i < TRandom() % 500; i++) { // Gets a random value of 0-500 in TaskF01()
56 for (i = 0; i < TRandom() % 500; i++) { // Gets a random value of 0-500 in TaskF01()
62 for (i = 0; i < TRandom() % 500; i++) { // Gets a random value of 0-500 in TaskF01()
97 LOS_TaskDelay(10); // 10, delay enouge time in Testcase()
100 …(g_ret1 == LOS_OK) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_OK)) { // pend-post-del ///post-pend-del in Testcase()
102 (g_ret3 == LOS_OK)) { // del-pend-post//del-post-pend in Testcase()
103 …(g_ret1 == LOS_OK) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_ERRNO_SEM_PENDED)) { // pend-delete-post in Testcase()
104 … ((g_ret1 == LOS_ERRNO_SEM_INVALID) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_OK)) { // post-del-pend in Testcase()
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| /kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/qlcnic/ |
| D | qlcnic_83xx_init.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
74 u16 delay; member
78 u16 delay;
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
151 adapter->ahw->idc.name[cur], in qlcnic_83xx_idc_log_state_history()
152 adapter->ahw->idc.name[prev]); in qlcnic_83xx_idc_log_state_history()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | gen6_engine_cs.c | 1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
40 * - Render Target Cache Flush Enable ([12] of DW1)
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| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
123 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
128 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
133 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
138 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
35 clock-names:
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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| /kernel/linux/linux-5.10/tools/power/pm-graph/config/ |
| D | suspend-x2-proc.cfg | 2 # Proc S3 (Suspend to Mem) x2 test - includes user processes
9 # sudo ./sleepgraph.py -config config/suspend-proc.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-x2-proc
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | freeze-dev.cfg | 2 # Dev S2 (Freeze) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/freeze-dev.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | standby-dev.cfg | 2 # Dev S1 (Standby) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/standby-dev.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
[all …]
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| D | suspend-dev.cfg | 2 # Dev S3 (Suspend to Mem) test - includes src calls / kernel threads
9 # sudo ./sleepgraph.py -config config/suspend-dev.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}-dev
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
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| D | standby-callgraph.cfg | 9 # sudo ./sleepgraph.py -config config/standby-callgraph.cfg
15 # ---- General Options ----
27 output-dir: standby-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
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| D | freeze-callgraph.cfg | 9 # sudo ./sleepgraph.py -config config/freeze-callgraph.cfg
15 # ---- General Options ----
27 output-dir: freeze-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
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| D | freeze.cfg | 9 # sudo ./sleepgraph.py -config config/freeze.cfg
14 # ---- General Options ----
26 output-dir: freeze-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
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| D | suspend.cfg | 9 # sudo ./sleepgraph.py -config config/suspend.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
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| D | standby.cfg | 9 # sudo ./sleepgraph.py -config config/standby.cfg
14 # ---- General Options ----
26 output-dir: standby-{hostname}-{date}-{time}
40 # ---- Advanced Options ----
57 # Back to Back Suspend Delay
58 # Time delay between the two test runs in ms (default: 0 ms)
61 # Pre Suspend Delay
62 # Include an N ms delay before (1st) suspend (default: 0 ms)
65 # Post Resume Delay
66 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
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| D | suspend-callgraph.cfg | 9 # sudo ./sleepgraph.py -config config/suspend.cfg
15 # ---- General Options ----
27 output-dir: suspend-{hostname}-{date}-{time}-cg
41 # ---- Advanced Options ----
58 # Back to Back Suspend Delay
59 # Time delay between the two test runs in ms (default: 0 ms)
62 # Pre Suspend Delay
63 # Include an N ms delay before (1st) suspend (default: 0 ms)
66 # Post Resume Delay
67 # Include an N ms delay after (last) resume (default: 0 ms)
[all …]
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| /kernel/liteos_a/testsuites/kernel/sample/kernel_base/ipc/event/smp/ |
| D | It_smp_los_event_032.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
51 PRINT_DEBUG("---000---\n"); in TaskF01()
58 PRINT_DEBUG("---111---\n"); in TaskF01()
65 PRINT_DEBUG("---222---\n"); in TaskF01()
94 TEST_TASK_PARAM_INIT(testTask, "it_event_032_task", TaskF01, TASK_PRIO_TEST - 1); in Testcase()
102 LOS_TaskDelay(10); // 10, delay enouge time in Testcase()
105 … ((g_ret1 == 0x11) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_OK)) { // pend-post-del ///post-pend-del in Testcase()
107 (g_ret3 == LOS_ERRNO_EVENT_SHOULD_NOT_DESTROY)) { // pend-delete-post in Testcase()
108 } else if ((g_ret1 == 0xff) && (g_ret2 == LOS_OK) && (g_ret3 == LOS_OK)) { // post-del-pend in Testcase()
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| /kernel/linux/linux-5.10/drivers/clk/ingenic/ |
| D | cgu.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits
37 * @od_max: the maximum post-VCO divider value
38 * @od_encoding: a pointer to an array mapping post-VCO divider values to
39 * their encoded values in the PLL control register, or -1 for
[all …]
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