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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sram/sram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic on-chip SRAM
10 - Rob Herring <robh@kernel.org>
15 Each child of the sram node specifies a region of reserved memory. Each
19 Following the generic-names recommended practice, node names should
25 pattern: "^sram(@.*)?"
30 - mmio-sram
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Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
19 "#address-cells":
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/kernel/liteos_a/kernel/include/
Dlos_builddef.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
55 #define LITE_OS_SEC_TEXT /* __attribute__((section(".text.sram"))) */
59 #define LITE_OS_SEC_TEXT_MINOR /* __attribute__((section(".text.ddr"))) */
63 #define LITE_OS_SEC_TEXT_INIT /* __attribute__((section(".text.init"))) */
67 #define LITE_OS_SEC_DATA /* __attribute__((section(".data.sram"))) */
71 #define LITE_OS_SEC_DATA_MINOR /* __attribute__((section(".data.ddr"))) */
75 #define LITE_OS_SEC_DATA_INIT /* __attribute__((section(".data.init"))) */
79 #define LITE_OS_SEC_BSS /* __attribute__((section(".bss.sram"))) */
83 #define LITE_OS_SEC_BSS_MINOR /* __attribute__((section(".bss.ddr"))) */
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/kernel/liteos_m/utils/
Dlos_compiler.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved.
202 * Vector table section
205 #define LITE_OS_SEC_VEC __attribute__ ((section(".vector")))
210 * .Text section (Code section)
213 #define LITE_OS_SEC_TEXT // __attribute__((section(".sram.text")))
218 * .Text.ddr section
221 #define LITE_OS_SEC_TEXT_MINOR // __attribute__((section(".dyn.text")))
226 * .Text.init section
229 #define LITE_OS_SEC_TEXT_INIT // __attribute__((section(".dyn.text")))
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&intc>;
13 osc24M: clk-24M {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <24000000>;
17 clock-output-names = "osc24M";
20 osc32k: clk-32k {
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Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
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Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
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Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
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Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
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/kernel/linux/linux-5.10/drivers/memory/
Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
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Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-tcon-top.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/thermal/thermal.h>
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Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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/kernel/liteos_m/tools/
Dmem_analysis.py2 # -*- coding: utf-8 -*-
5 # Copyright (c) 2020-2022 Huawei Device Co., Ltd.
10 # http://www.apache.org/licenses/LICENSE-2.0
45 def storage_static_data(offset, section, sizeHex, symbol, lib, obj): argument
48 static_map[g_row_num] = {'offsets' : "offsets", 'section' : "section",\
54 static_map[g_row_num] = {'offsets': offset, 'section' : section,\
66 c.value = values.get('section')
77 wb.save('static_symbol-%s.xlsx' % datetime.datetime.now().strftime('%Y-%m-%d %H_%M_%S'))
86 target_list.append('{:<30s}'.format(values.get('section')))
155 wb.save('dync_mem-%s.xlsx' % datetime.datetime.now().strftime('%Y-%m-%d %H_%M_%S'))
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/kernel/linux/linux-5.10/arch/arm/mach-rockchip/
Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/kernel/linux/linux-5.10/arch/csky/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
119 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
162 # VA_BITS - PAGE_SHIFT - 3
196 prompt "C-SKY PMU type"
226 bool "Tightly-Coupled/Sram Memory"
229 The implementation are not only used by TCM (Tightly-Coupled Meory)
230 but also used by sram on SOC bus. It follow existed linux tcm
232 re-used directly.
276 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
281 int "Maximum number of CPUs (2-32)"
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/kernel/linux/linux-5.10/Documentation/driver-api/memory-devices/
Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
/kernel/linux/linux-5.10/sound/soc/intel/catpt/
Ddsp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
19 return param == chan->device->dev; in catpt_dma_filter()
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); in catpt_dma_request_config_chan()
41 dev_err(cdev->dev, "request channel failed\n"); in catpt_dma_request_config_chan()
42 return ERR_PTR(-ENODEV); in catpt_dma_request_config_chan()
54 dev_err(cdev->dev, "slave config failed: %d\n", ret); in catpt_dma_request_config_chan()
73 dev_err(cdev->dev, "prep dma memcpy failed\n"); in catpt_dma_memcpy()
74 return -EIO; in catpt_dma_memcpy()
79 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), in catpt_dma_memcpy()
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/kernel/linux/linux-5.10/drivers/atm/
Dnicstar.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 have 32K x 32bit SRAM, in which case
48 128K x 32bit SRAM will limit the maximum
56 #define NUM_HB 8 /* Pre-allocated huge buffers */
107 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
108 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
111 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
112 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
114 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
122 * RSQ - Receive Status Queue
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/kernel/linux/linux-5.10/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
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/kernel/liteos_a/tools/build/
Dliteos.ld2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
50 /* .ARM.exidx is sorted, so has to go in its own output section. */
53 /* text/read-only data */
56 *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
117 * but not aligned to the next section necessarily.
153 * but not aligned to the next section necessarily.
176 __user_init_size = __user_init_end - __user_init_entry;
Dliteos_llvm.ld2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
62 /* .ARM.exidx is sorted, so has to go in its own output section. */
68 /* text/read-only data */
71 *(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
132 * but not aligned to the next section necessarily.
158 * but not aligned to the next section necessarily.
181 __user_init_size = __user_init_end - __user_init_entry;
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2012 Freescale Semiconductor, Inc
51 unsigned int eccread; /* Non zero for a full-page ECC read */
67 .offs = 2, /* 0 on 8-bit small page */
77 .offs = 2, /* 0 on 8-bit small page */
84 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section, in fsl_ifc_ooblayout_ecc() argument
89 if (section) in fsl_ifc_ooblayout_ecc()
90 return -ERANGE; in fsl_ifc_ooblayout_ecc()
92 oobregion->offset = 8; in fsl_ifc_ooblayout_ecc()
93 oobregion->length = chip->ecc.total; in fsl_ifc_ooblayout_ecc()
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/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/
Dimg.h8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2008 - 2014, 2018 - 2020 Intel Corporation
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2008 - 2014, 2018 - 2020 Intel Corporation
67 #include "api/dbg-tlv.h"
70 #include "error-dump.h"
91 * enumeration of ucode section.
94 * first one packaged into the firmware file is the DATA section and
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/kernel/linux/linux-5.10/Documentation/driver-api/
Dmen-chameleon-bus.rst30 ----------------------
37 -----------------------------------------
43 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
44 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
46 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
47 per MCB device like PCIe based carriers with MSI or MSI-X support.
54 - The MEN Chameleon Bus itself,
55 - drivers for MCB Carrier Devices and
56 - the parser for the Chameleon table.
59 -----------------
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