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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - ti,j721e-pcie-ep
24 reg-names:
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Dti,j721e-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - ti,j721e-pcie-host
24 reg-names:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
Dpci-dra7xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
27 #include <linux/mfd/syscon.h>
32 #include "pcie-designware.h"
34 /* PCIe controller wrapper DRA7XX configuration registers */
90 int phy_count; /* DT phy-names count */
101 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
103 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) in dra7xx_pcie_readl() argument
105 return readl(pcie->base + offset); in dra7xx_pcie_readl()
[all …]
Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
16 #include <linux/mfd/syscon.h>
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
35 #include "pcie-designware.h"
43 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
70 struct clk *pcie; member
85 /* power domain for pcie */
87 /* power domain for pcie phy */
[all …]
Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Kirin Phone SoCs
17 #include <linux/mfd/syscon.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
33 /* PCIe ELBI registers */
63 /* peri_crg ctrl */
99 writel(val, kirin_pcie->apb_base + reg); in kirin_apb_ctrl_writel()
104 return readl(kirin_pcie->apb_base + reg); in kirin_apb_ctrl_readl()
111 writel(val, kirin_pcie->phy_base + reg); in kirin_apb_phy_writel()
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/cadence/
Dpci-j721e.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
14 #include <linux/mfd/syscon.h>
22 #include "pcie-cadence.h"
74 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_user_readl() argument
76 return readl(pcie->user_cfg_base + offset); in j721e_pcie_user_readl()
79 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, in j721e_pcie_user_writel() argument
82 writel(value, pcie->user_cfg_base + offset); in j721e_pcie_user_writel()
85 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) in j721e_pcie_intd_readl() argument
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
[all …]
Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
43 #address-cells = <1>;
44 #size-cells = <0>;
45 enable-method = "aspeed,ast2600-smp";
[all …]
Daspeed-g5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
36 #address-cells = <1>;
37 #size-cells = <0>;
40 compatible = "arm,arm1176jzf-s";
52 compatible = "simple-bus";
[all …]
Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
[all …]
Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
[all …]
/kernel/linux/linux-5.10/drivers/pci/controller/mobiveil/
Dpcie-layerscape-gen4.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
5 * Copyright 2019-2020 NXP
20 #include <linux/mfd/syscon.h>
23 #include "pcie-mobiveil.h"
37 #define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
45 static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) in ls_pcie_g4_lut_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); in ls_pcie_g4_lut_readl()
50 static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, in ls_pcie_g4_lut_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off); in ls_pcie_g4_lut_writel()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
[all …]
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/kernel/linux/linux-5.10/drivers/phy/ti/
Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
21 #include <linux/mfd/syscon.h>
174 struct regmap *phy_power_syscon; /* ctrl. reg. acces */
175 struct regmap *pcs_syscon; /* ctrl. reg. acces */
176 struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
177 unsigned int dpll_reset_reg; /* reg. index within syscon */
178 unsigned int power_reg; /* power reg. index within syscon */
179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
/kernel/linux/linux-5.10/drivers/phy/mscc/
Dphy-ocelot-serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/mfd/syscon.h>
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
29 /* Not used when in QSGMII or PCIe mode */
31 struct serdes_ctrl *ctrl; member
406 return -EOPNOTSUPP; in serdes_set_mode()
409 if (macro->idx != ocelot_serdes_muxes[i].idx || in serdes_set_mode()
415 macro->port != ocelot_serdes_muxes[i].port) in serdes_set_mode()
418 ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG, in serdes_set_mode()
424 if (macro->idx <= SERDES1G_MAX) in serdes_set_mode()
[all …]
/kernel/linux/linux-5.10/drivers/soc/aspeed/
Daspeed-p2a-ctrl.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <linux/mfd/syscon.h>
28 #include <linux/aspeed-p2a-ctrl.h>
30 #define DEVICE_NAME "aspeed-p2a-ctrl"
34 /* SCU180 is the PCIe Configuration Setting Control Register. */
91 regmap_update_bits(p2a_ctrl->regmap, in aspeed_p2a_enable_bridge()
97 regmap_update_bits(p2a_ctrl->regmap, SCU180, SCU180_ENP2A, 0); in aspeed_p2a_disable_bridge()
104 struct aspeed_p2a_user *priv = file->private_data; in aspeed_p2a_mmap()
105 struct aspeed_p2a_ctrl *ctrl = priv->parent; in aspeed_p2a_mmap() local
107 if (ctrl->mem_base == 0 && ctrl->mem_size == 0) in aspeed_p2a_mmap()
[all …]
/kernel/linux/linux-5.10/drivers/phy/lantiq/
Dphy-lantiq-vrx200-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
8 * Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
18 #include <linux/mfd/syscon.h>
27 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
[all …]

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