Home
last modified time | relevance | path

Searched +full:watchdog +full:- +full:timers (Results 1 – 25 of 139) sorted by relevance

123456

/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddra7-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
11 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
18 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
25 ti,timers = <&timer3>;
26 ti,watchdog-timers = <&timer4>, <&timer9>;
31 ti,timers = <&timer11>;
32 ti,watchdog-timers = <&timer7>, <&timer8>;
37 ti,timers = <&timer5>;
38 ti,watchdog-timers = <&timer10>;
Ddra74-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "dra7-ipu-dsp-common.dtsi"
9 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
16 ti,timers = <&timer6>;
17 ti,watchdog-timers = <&timer13>;
Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
[all …]
Ds3c2416.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/s3c2443.h>
10 #include "s3c2416-pinctrl.dtsi"
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,arm926ej-s";
31 clocks: clock-controller@4c000000 {
32 compatible = "samsung,s3c2416-clock";
34 #clock-cells = <1>;
38 compatible = "samsung,s3c2440-uart";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/kernel/linux/linux-5.10/drivers/remoteproc/
Domap_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * Ohad Ben-Cohen <ohad@wizery.com>
12 * Suman Anna <s-anna@ti.com>
13 * Hari Kanigeri <h-kanigeri2@ti.com>
26 #include <linux/dma-mapping.h>
30 #include <linux/omap-iommu.h>
31 #include <linux/omap-mailbox.h>
35 #include <clocksource/timer-ti-dm.h>
37 #include <linux/platform_data/dmtimer-omap.h>
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dti,davinci-timer.txt3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
6 timers, each half can operate in conjunction (chain mode) or independently
9 The timer is a free running up-counter and can generate interrupts when the
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
13 watchdog timers.
17 - compatible : should be "ti,da830-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupts generated by the timer.
[all …]
/kernel/linux/linux-5.10/drivers/watchdog/
Di6300esb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
21 * Change driver to use the watchdog subsystem
35 #include <linux/watchdog.h>
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
[all …]
Dsp805_wdt.c2 * drivers/char/watchdog/sp805-wdt.c
4 * Watchdog driver for ARM SP805 watchdog module
31 #include <linux/watchdog.h>
36 #define MODULE_NAME "sp805-wdt"
38 /* watchdog register offsets and masks */
79 "Set to 1 to keep watchdog running after device release");
85 u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL); in wdt_is_running()
96 rate = wdt->rate; in wdt_setload()
104 load = div_u64(rate, 2) * timeout - 1; in wdt_setload()
109 spin_lock(&wdt->lock); in wdt_setload()
[all …]
Dgeodewdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Watchdog timer for machines with the CS5535/CS5536 companion chip
4 * Copyright (C) 2006-2007, Advanced Micro Devices, Inc.
14 #include <linux/watchdog.h>
36 "Watchdog timeout in seconds. 1<= timeout <=131, default="
42 "Watchdog cannot be stopped once started (default="
71 return -EINVAL; in geodewdt_set_heartbeat()
85 return -EBUSY; in geodewdt_open()
100 pr_crit("Unexpected close - watchdog is not stopping\n"); in geodewdt_release()
123 return -EFAULT; in geodewdt_write()
[all …]
Dcpwd.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpwd.c - driver implementation for hardware watchdog
3 * timers found on Sun Microsystems CP1400 and CP1500 boards.
5 * This device supports both the generic Linux watchdog
6 * interface and Solaris-compatible ioctls as best it is
38 #include <asm/watchdog.h>
42 #define WD_OBPNAME "watchdog"
43 #define WD_BADMODEL "SUNW,501-5336"
60 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
61 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
[all …]
Dit87_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Watchdog Timer Driver
4 * for ITE IT87xx Environment Control - Low Pin Count Input / Output
12 * Data-sheets: Publicly available at the ITE website
15 * Support of the watchdog timers, which are available on
29 #include <linux/watchdog.h>
94 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default="
97 MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default="
100 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default="
111 return -EBUSY; in superio_enter()
[all …]
/kernel/linux/linux-5.10/Documentation/mips/
Dingenic-tcu.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
9 counters, timers, or PWM.
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Datmel-wdt.txt1 * Atmel Watchdog Timers
3 ** at91sam9-wdt
6 - compatible: must be "atmel,at91sam9260-wdt".
7 - reg: physical base address of the controller and length of memory mapped
9 - clocks: phandle to input clock.
12 - timeout-sec: contains the watchdog timeout in seconds.
13 - interrupts : Should contain WDT interrupt.
14 - atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in
17 - atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in
18 seconds. This value must be smaller than the max-heartbeat-sec value.
[all …]
Dmt7621-wdt.txt1 Ralink Watchdog Timers
4 - compatible: must be "mediatek,mt7621-wdt"
5 - reg: physical base address of the controller and length of the register range
9 watchdog@100 {
10 compatible = "mediatek,mt7621-wdt";
Drt2880-wdt.txt1 Ralink Watchdog Timers
4 - compatible: must be "ralink,rt2880-wdt"
5 - reg: physical base address of the controller and length of the register range
8 - interrupts: Specify the INTC interrupt number
12 watchdog@120 {
13 compatible = "ralink,rt2880-wdt";
16 interrupt-parent = <&intc>;
/kernel/linux/linux-5.10/arch/sparc/include/uapi/asm/
Dwatchdog.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * watchdog - Driver interface for the hardware watchdog timers
14 #include <linux/watchdog.h>
16 /* Solaris compatibility ioctls--
17 * Ref. <linux/watchdog.h> for standard linux watchdog ioctls
/kernel/linux/linux-5.10/drivers/acpi/arm64/
Dgtdt.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * struct acpi_gtdt_descriptor - Store the key info of GTDT for all functions
43 platform_timer += gh->length; in next_platform_timer()
58 return gh->type == ACPI_GTDT_TYPE_TIMER_BLOCK; in is_timer_block()
66 if (gh->type != ACPI_GTDT_TYPE_WATCHDOG) in is_non_secure_watchdog()
69 return !(wd->timer_flags & ACPI_GTDT_WATCHDOG_SECURE); in is_non_secure_watchdog()
86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
90 * So we only handle the non-secure timer PPIs,
101 return map_gt_gsi(gtdt->non_secure_el1_interrupt, in acpi_gtdt_map_ppi()
102 gtdt->non_secure_el1_flags); in acpi_gtdt_map_ppi()
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlp-hal/
Dpic.h2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
46 #define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47 #define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48 #define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49 #define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50 #define PIC_CTRL_WTE 0 /* watchdog timer enable */
56 #define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57 #define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
352 /* Ack the Status register for Watchdog & System timers */ in nlm_pic_ack()
/kernel/linux/linux-5.10/Documentation/watchdog/
Dwdt.rst2 WDT Watchdog Timer Interfaces For The Linux Operating System
9 - ICS WDT501-P
10 - ICS WDT501-P (no fan tachometer)
11 - ICS WDT500-P
13 All the interfaces provide /dev/watchdog, which when open must be written
15 time another timeout. In the case of the software watchdog the ability to
17 boards physically pull the machine down off their own onboard timers and
26 The ICS ISA-bus wdt card cannot be safely probed for. Instead you need to
34 heartbeat Watchdog heartbeat in seconds (default 60)
35 nowayout Watchdog cannot be stopped once started (kernel
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
[all …]
/kernel/linux/linux-5.10/arch/x86/platform/intel-mid/
Dintel-mid.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel-mid.c: Intel MID platform setup code
27 #include <asm/intel-mid.h>
41 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
51 * lapic (with C3STOP) --------- 100
52 * apbt (always-on) ------------ 110
53 * lapic (always-on,ARAT) ------ 150
90 x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer; in intel_mid_time_init()
97 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; in intel_mid_time_init()
102 x86_init.timers.setup_percpu_clockev = apbt_time_init; in intel_mid_time_init()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
40 pllctrl: pll-controller@2310000 {
41 compatible = "ti,keystone-pllctrl", "syscon";
45 devctrl: device-state-control@2620000 {
[all …]
/kernel/linux/linux-5.10/Documentation/admin-guide/
Dkernel-per-CPU-kthreads.rst2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
13 - Documentation/core-api/irq/irq-affinity.rst: Binding interrupts to sets of CPUs.
15 - Documentation/admin-guide/cgroup-v1: Using cgroups to bind tasks to sets of CPUs.
17 - man taskset: Using the taskset command to bind tasks to sets
20 - man sched_setaffinity: Using the sched_setaffinity() system
23 - /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
26 - In order to locate kernel-generated OS jitter on CPU N:
[all …]
/kernel/linux/linux-5.10/kernel/time/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 # Watchdog function for clocksources to detect instabilities
21 # cycle update - x86/TSC misfeature
37 # Architecture can handle broadcast in a driver-agnostic way
55 # Select to handle posix CPU timers from task_work
65 menu "Timers subsystem"
94 will only trigger on an as-needed basis when the system is idle.
122 This is implemented at the expense of some overhead in user <-> kernel
138 The major pre-requirement for full dynticks to work is to

123456