Lines Matching full:clock

4 Sources of clock signal can be represented by any node in the device
5 tree.  Those nodes are designated as clock providers.  Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs.  Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device.  The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells:	   Number of cells in a clock specifier; Typically 0 for nodes
18 		   with a single clock output and 1 for nodes with multiple
19 		   clock outputs.
22 clock-output-names: Recommended to be a list of strings of clock output signal
23 		    names indexed by the first cell in the clock specifier.
24 		    However, the meaning of clock-output-names is domain
25 		    specific to the clock provider, and is only provided to
26 		    encourage using the same meaning for the majority of clock
27 		    providers.  This format may not work for clock providers
28 		    using a complex clock specifier format.  In those cases it
32 		    Clock consumer nodes must never directly reference
33 		    the provider's clock-output-names property.
38         #clock-cells = <1>;
39         clock-output-names = "ckil", "ckih";
42 - this node defines a device with two clock outputs, the first named
44   clocks by index. The names should reflect the clock output signal
47 clock-indices:	   If the identifying number for the clocks in the node
49 		   identifiers into the clock-output-names array.
55 		#clock-cells = <1>;
56 		clock-indices = <1>, <3>;
57 		clock-output-names = "clka", "clkb";
60 	This ensures we do not have any empty strings in clock-output-names
63 ==Clock consumers==
66 clocks:		List of phandle and clock specifier pairs, one pair
67 		for each clock input to the device.  Note: if the
68 		clock provider specifies '0' for #clock-cells, then
72 clock-names:	List of clock input name strings sorted in the same
74 		will use clock-names to match clock input names
76 clock-ranges:	Empty property indicating that child nodes can inherit named
78 		clock to their children.
84         clock-names = "baud", "register";
88 This represents a device with two clock inputs, named "baud" and "register".
89 The baud clock is connected to output 1 of the &osc device, and the register
90 clock is connected to output 0 of the &ref.
96         compatible = "fixed-clock";
97         #clock-cells = <0>;
98         clock-frequency  = <32678>;
99         clock-output-names = "osc";
102     /* phase-locked-loop device, generates a higher frequency clock
106         #clock-cells = <1>;
108         clock-names = "ref";
110         clock-output-names = "pll", "pll-switched";
113     /* UART, using the low frequency oscillator for the baud clock,
121         clock-names = "baud", "register";
125 low-frequency reference clock, a PLL device to generate a higher frequency
126 clock signal, and a UART.
128 * The oscillator is fixed-frequency, and provides one clock output, named "osc".
129 * The PLL is both a clock provider and a clock consumer. It uses the clock
132 * The UART has its baud clock connected the external oscillator and its
133   register clock connected to the PLL clock (the "pll-switched" signal)
135 ==Assigned clock parents and rates==
138 and clock frequencies. Such a configuration can be specified in a device tree
139 node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
140 properties. The assigned-clock-parents property should contain a list of parent
141 clocks in the form of a phandle and clock specifier pair and the
142 assigned-clock-rates property should contain a list of frequencies in Hz. Both
146 To skip setting parent or rate of a clock its corresponding entry should be
154         clock-names = "baud", "register";
157         assigned-clock-parents = <&pll 2>;
158         assigned-clock-rates = <0>, <460800>;
161 In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
162 the <&pll 2> clock is assigned a frequency value of 460800 Hz.
164 Configuring a clock's parent and rate through the device node that consumes
165 the clock can be done only for clocks that have a single user. Specifying
167 a shared clock is forbidden.
170 be similarly specified in the clock provider node.
177 protected-clocks property in the form of a clock specifier list. This property should
180    clock-controller@a000f000 {