Lines Matching full:clock
1 Imagination Technologies Pistachio SoC clock controllers
4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
25 - reg: Must contain the base address and length of the core clock controller.
26 - #clock-cells: Must be 1. The single cell is the clock identifier.
27 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
28 - clocks: Must contain an entry for each clock in clock-names.
29 - clock-names: Must include "xtal" (see "External clocks") and
34 clk_core: clock-controller@18144000 {
39 clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
41 #clock-cells = <1>;
44 Peripheral clock controller:
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
53 - reg: Must contain the base address and length of the peripheral clock
55 - #clock-cells: Must be 1. The single cell is the clock identifier.
56 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
57 - clocks: Must contain an entry for each clock in clock-names.
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
59 by the core clock controller.
62 clk_periph: clock-controller@18144800 {
66 clock-names = "periph_sys";
68 #clock-cells = <1>;
76 control registers. The system clock ("sys") generated by the peripheral clock
77 controller is the input clock to the system clock controller.
83 - #clock-cells: Must be 1. The single cell is the clock identifier.
84 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
85 - clocks: Must contain an entry for each clock in clock-names.
86 - clock-names: Must include "sys", the system clock generated by the peripheral
87 clock controller.
94 clock-names = "sys";
96 #clock-cells = <1>;
109 - clocks: Must contain an entry for each clock in clock-names.
110 - clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
112 - #clock-cells: Must be 1. The single cell is the clock identifier.
113 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
120 clock-names = "audio_clk_in", "enet_clk_in";
122 #clock-cells = <1>;