Lines Matching +full:0 +full:x238
50 Default is 0.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
53 Default is 0x8.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
56 Default is 0x0.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
65 clocks = <&refclk 0>;
67 reg = <0x0 0x17000100 0x0 0x1000>;
69 type = <0>;
75 clocks = <&pmdpll 0>;
76 reg = <0x0 0x7e200200 0x0 0x10>;
83 clocks = <&refclk 0>;
85 reg = <0x0 0x17000120 0x0 0x1000>;
93 clocks = <&socplldiv2 0>;
95 reg = <0x0 0x1703C000 0x0 0x1000>;
103 clocks = <&socplldiv2 0>;
105 reg = <0x0 0x17000000 0x0 0x1000>;
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
116 clocks = <&ahbclk 0>;
118 reg = <0x0 0x1F2AC000 0x0 0x1000
119 0x0 0x1F2AC000 0x0 0x1000>;
121 csr-offset = <0x0>;
122 csr-mask = <0x200>;
123 enable-offset = <0x8>;
124 enable-mask = <0x200>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
128 flags = <0x8>;