Lines Matching +full:imx51 +full:- +full:uart
4 - compatible : Should be one of
5 "fsl,imx25-sdma"
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8 "fsl,imx51-sdma"
9 "fsl,imx53-sdma"
10 "fsl,imx6q-sdma"
11 "fsl,imx7d-sdma"
12 "fsl,imx8mq-sdma"
13 "fsl,imx8mm-sdma"
14 "fsl,imx8mn-sdma"
15 "fsl,imx8mp-sdma"
16 The -to variants should be preferred since they allow to determine the
19 - reg : Should contain SDMA registers location and length
20 - interrupts : Should contain SDMA interrupt
21 - #dma-cells : Must be <3>.
24 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
31 ---------------------
36 4 MCU domain UART
37 5 Shared UART
61 -------------------------
68 - gpr : The phandle to the General Purpose Register (GPR) node.
69 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
78 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
81 #dma-cells = <3>;
82 fsl,sdma-ram-script-name = "sdma-imx51.bin";
91 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
97 dma-names = "rx", "tx";
98 fsl,fifo-depth = <15>;
101 Using the fsl,sdma-event-remap property:
108 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
111 The fsl,sdma-event-remap property in this case has two values:
112 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
115 - <0 16 1> means that the offset is 0, so GPR0 is the register of the