Lines Matching +full:interrupt +full:- +full:controller

1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
15   source connected to this controller. The value shall be 2.
16 - interrupts: Specifies the list of interrupt lines which are handled by
17   the interrupt controller in the parent controller's notation. Interrupts
18   are mapped one-to-one to parent interrupts.
21 -------
23 intc: interrupt-controller {	/* Parent interrupt controller */
24 	interrupt-controller;
25 	#interrupt-cells = <1>;	/* For example below */
29 tb10x_ictl: pic@2000 {		/* TB10x interrupt controller */
30 	compatible = "abilis,tb10x-ictl";
32 	interrupt-controller;
33 	#interrupt-cells = <2>;
34 	interrupt-parent = <&intc>;