Lines Matching +full:rgmii +full:- +full:id

1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11   - $ref: "ethernet-controller.yaml#"
14   - Dan Murphy <dmurphy@ti.com>
18   transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19   and 1000BASE-T Ethernet protocols.
25   Media Independent Interface (GMII) or Reduced GMII (RGMII).
34   ti,min-output-impedance:
40   ti,max-output-impedance:
45       Note: ti,min-output-impedance and ti,max-output-impedance are mutually
46         exclusive. When both properties are present ti,max-output-impedance
49   tx-fifo-depth:
52        Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
54   rx-fifo-depth:
57        Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
59   ti,clk-output-sel:
62       Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
66   ti,rx-internal-delay:
69       RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
73   ti,tx-internal-delay:
76       RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
83           PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
85           should use "rgmii-id" if internal delays are desired as this may be
86           changed in future to cause "rgmii" mode to disable delays.
88   ti,dp83867-rxctrl-strap-quirk:
96   ti,sgmii-ref-clock-output-enable:
99       This denotes which SGMII configuration is used (4 or 6-wire modes).
102   ti,fifo-depth:
106       Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
110   - reg
115   - |
116     #include <dt-bindings/net/ti-dp83867.h>
118       #address-cells = <1>;
119       #size-cells = <0>;
120       ethphy0: ethernet-phy@0 {
122         tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
123         rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
124         ti,max-output-impedance;
125         ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
126         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
127         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;