Lines Matching +full:imx8mq +full:- +full:reset
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible:
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
14 - interrupts: A list of interrupt outputs of the controller. Must contain an
15 entry for each entry in the interrupt-names property.
16 - interrupt-names: Must include the following entries:
17 - "msi": The interrupt that is asserted when an MSI is received
18 - clock-names: Must include the following additional entries:
19 - "pcie_phy"
22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
24 - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
25 - fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
26 - fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
27 - fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
31 - reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
32 signal. It's not polarity aware and defaults to active-low reset sequence
33 (L=reset state, H=operation state).
34 - reset-gpio-active-high: If present then the reset sequence using the GPIO
35 specified in the "reset-gpio" property is reversed (H=reset state,
37 - vpcie-supply: Should specify the regulator in charge of PCIe port power.
42 Additional required properties for imx6sx-pcie:
43 - clock names: Must include the following additional entries:
44 - "pcie_inbound_axi"
45 - power-domains: Must be set to phandles pointing to the DISPLAY and
47 - power-domain-names: Must be "pcie", "pcie_phy"
49 Additional required properties for imx7d-pcie and imx8mq-pcie:
50 - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
51 - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
53 - reset-names: Must contain the following entries:
54 - "pciephy"
55 - "apps"
56 - "turnoff"
57 - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
59 Additional required properties for imx8mq-pcie:
60 - clock-names: Must include the following additional entries:
61 - "pcie_aux"
66 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
69 reg-names = "dbi", "config";
70 #address-cells = <3>;
71 #size-cells = <2>;
76 num-lanes = <1>;
78 interrupt-names = "msi";
79 #interrupt-cells = <1>;
80 interrupt-map-mask = <0 0 0 0x7>;
81 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
86 clock-names = "pcie", "pcie_bus", "pcie_phy";
92 PCI-e controller via the fsl,imx7d-pcie-phy phandle.
95 - compatible:
96 - "fsl,imx7d-pcie-phy"
97 - reg: base address and length of the PCIe PHY controller