Lines Matching +full:- +full:pinmux

1 NVIDIA Tegra124 pinmux controller
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: For Tegra124, must contain "nvidia,tegra124-pinmux".  For
10   Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
11 - reg: Should contain a list of base address and size pairs for:
12     -- first entry - the drive strength and pad control registers.
13     -- second entry - the pinmux registers
14     -- third entry - the MIPI_PAD_CTRL register
18 	include/dt-binding/pinctrl/pinctrl-tegra.h.
19 - nvidia,enable-input: Integer. Enable the pin's input path.
22 - nvidia,open-drain: Integer.
25 - nvidia,lock: Integer. Lock the pin configuration against further changes
29 - nvidia,io-reset: Integer. Reset the IO path.
32 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
41   per-pin mux groups:
44     nvidia,enable-input. Some support nvidia,lock nvidia,open-drain,
45     nvidia,io-reset and nvidia,rcv-sel.
87     These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
88     nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
89     support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
90     and nvidia,drive-type.
116 	pinmux: pinmux {
117 		compatible = "nvidia,tegra124-pinmux";
123 Example pinmux entries:
126 		sdmmc4_default: pinmux {
151 		pinctrl-names = "default";
152 		pinctrl-0 = <&sdmmc4_default>;