Lines Matching +full:- +full:pinmux

1 NVIDIA Tegra194 pinmux controller
4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6   - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7   - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
17 parameters, such as pull-up, tristate, drive strength, etc.
21 include/dt-binding/pinctrl/pinctrl-tegra.h.
23 Required subnode-properties:
24 - nvidia,pins : An array of strings. Each string contains the name of a pin or
27 Optional subnode-properties:
28 - nvidia,function: A string containing the name of the function to mux to the
30 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
32 - nvidia,tristate: Integer.
34 - nvidia,enable-input: Integer. Enable the pin's input path.
37 - nvidia,open-drain: Integer.
40 - nvidia,lock: Integer. Lock the pin configuration against further changes
44 - nvidia,io-hv: Integer. Select high-voltage receivers.
47 - nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
50 - nvidia,drive-type: Integer. Valid range 0...3.
51 - nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
54 - nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
60     These correspond to Tegra PADCTL_* (pinmux) registers.
64     These correspond to Tegra PADCTL_* (pinmux) registers. Any property
72     See the list above for the pin name to use when configuring the pinmux.
88 		tegra_pinctrl: pinmux: pinmux@2430000 {
89 			compatible = "nvidia,tegra194-pinmux";
93 			pinctrl-names = "pex_rst";
94 			pinctrl-0 = <&pex_rst_c5_out_state>;
101 					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
102 					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;