Lines Matching +full:0 +full:x020bc000
58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
111 #clock-cells = <0>;
112 clock-frequency = <0>;
118 #clock-cells = <0>;
119 clock-frequency = <0>;
125 #clock-cells = <0>;
126 clock-frequency = <0>;
132 #clock-cells = <0>;
133 clock-frequency = <0>;
151 #phy-cells = <0>;
163 reg = <0x008f8000 0x4000>;
169 reg = <0x00900000 0x20000>;
177 reg = <0x00a01000 0x1000>,
178 <0x00a00100 0x100>;
184 reg = <0x00a02000 0x1000>;
194 reg = <0x01800000 0x4000>;
205 reg = <0x01804000 0x2000>;
220 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
231 dmas = <&dma_apbh 0>;
240 reg = <0x02000000 0x100000>;
247 reg = <0x02000000 0x40000>;
252 reg = <0x02004000 0x4000>;
254 dmas = <&sdma 14 18 0>,
255 <&sdma 15 18 0>;
260 <&clks 0>, <&clks 0>, <&clks 0>,
262 <&clks 0>, <&clks 0>,
274 #size-cells = <0>;
276 reg = <0x02008000 0x4000>;
286 #size-cells = <0>;
288 reg = <0x0200c000 0x4000>;
298 #size-cells = <0>;
300 reg = <0x02010000 0x4000>;
310 #size-cells = <0>;
312 reg = <0x02014000 0x4000>;
323 reg = <0x02020000 0x4000>;
328 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
335 reg = <0x02024000 0x4000>;
344 dmas = <&sdma 23 21 0>,
345 <&sdma 24 21 0>;
351 #sound-dai-cells = <0>;
353 reg = <0x02028000 0x4000>;
358 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
365 #sound-dai-cells = <0>;
367 reg = <0x0202c000 0x4000>;
372 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
379 #sound-dai-cells = <0>;
381 reg = <0x02030000 0x4000>;
386 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
394 reg = <0x02034000 0x4000>;
397 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
398 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
399 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
400 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
401 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
421 reg = <0x02080000 0x4000>;
431 reg = <0x02084000 0x4000>;
441 reg = <0x02088000 0x4000>;
451 reg = <0x0208c000 0x4000>;
461 reg = <0x02090000 0x4000>;
466 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
472 reg = <0x02094000 0x4000>;
477 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
483 reg = <0x02098000 0x4000>;
492 reg = <0x0209c000 0x4000>;
499 gpio-ranges = <&iomuxc 0 5 26>;
504 reg = <0x020a0000 0x4000>;
511 gpio-ranges = <&iomuxc 0 31 20>;
516 reg = <0x020a4000 0x4000>;
523 gpio-ranges = <&iomuxc 0 51 29>;
528 reg = <0x020a8000 0x4000>;
535 gpio-ranges = <&iomuxc 0 80 32>;
540 reg = <0x020ac000 0x4000>;
547 gpio-ranges = <&iomuxc 0 112 24>;
552 reg = <0x020b0000 0x4000>;
559 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
564 reg = <0x020b4000 0x4000>;
571 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
576 reg = <0x020b8000 0x4000>;
584 reg = <0x020bc000 0x4000>;
591 reg = <0x020c0000 0x4000>;
599 reg = <0x020c4000 0x4000>;
610 reg = <0x020c8000 0x1000>;
621 anatop-reg-offset = <0x110>;
627 anatop-enable-bit = <0>;
636 anatop-reg-offset = <0x120>;
639 anatop-min-bit-val = <0>;
642 anatop-enable-bit = <0>;
651 anatop-reg-offset = <0x130>;
654 anatop-min-bit-val = <0>;
657 anatop-enable-bit = <0>;
666 anatop-reg-offset = <0x140>;
667 anatop-vol-bit-shift = <0>;
669 anatop-delay-reg-offset = <0x170>;
682 anatop-reg-offset = <0x140>;
685 anatop-delay-reg-offset = <0x170>;
699 anatop-reg-offset = <0x140>;
702 anatop-delay-reg-offset = <0x170>;
723 reg = <0x020c9000 0x1000>;
731 reg = <0x020ca000 0x1000>;
738 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
739 reg = <0x020cc000 0x4000>;
742 compatible = "fsl,sec-v4.0-mon-rtc-lp";
744 offset = <0x34>;
751 offset = <0x38>;
752 value = <0x60>;
753 mask = <0x60>;
758 compatible = "fsl,sec-v4.0-pwrkey";
768 reg = <0x020d0000 0x4000>;
773 reg = <0x020d4000 0x4000>;
779 reg = <0x020d8000 0x4000>;
787 reg = <0x020dc000 0x4000>;
797 #size-cells = <0>;
799 power-domain@0 {
800 reg = <0>;
801 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
813 #power-domain-cells = <0>;
825 #power-domain-cells = <0>;
833 reg = <0x020e0000 0x4000>;
839 reg = <0x020e4000 0x4000>;
844 reg = <0x020ec000 0x4000>;
859 reg = <0x02100000 0x100000>;
863 compatible = "fsl,sec-v4.0";
866 reg = <0x2100000 0x10000>;
867 ranges = <0 0x2100000 0x10000>;
876 compatible = "fsl,sec-v4.0-job-ring";
877 reg = <0x1000 0x1000>;
882 compatible = "fsl,sec-v4.0-job-ring";
883 reg = <0x2000 0x1000>;
890 reg = <0x02184000 0x200>;
894 fsl,usbmisc = <&usbmisc 0>;
896 ahb-burst-config = <0x0>;
897 tx-burst-size-dword = <0x10>;
898 rx-burst-size-dword = <0x10>;
904 reg = <0x02184200 0x200>;
909 ahb-burst-config = <0x0>;
910 tx-burst-size-dword = <0x10>;
911 rx-burst-size-dword = <0x10>;
917 reg = <0x02184400 0x200>;
925 ahb-burst-config = <0x0>;
926 tx-burst-size-dword = <0x10>;
927 rx-burst-size-dword = <0x10>;
934 reg = <0x02184800 0x200>;
940 reg = <0x02188000 0x4000>;
953 fsl,stop-mode = <&gpr 0x10 3>;
958 reg = <0x0218c000 0x4000>;
968 reg = <0x02190000 0x4000>;
980 reg = <0x02194000 0x4000>;
992 reg = <0x02198000 0x4000>;
1004 reg = <0x0219c000 0x4000>;
1016 #size-cells = <0>;
1018 reg = <0x021a0000 0x4000>;
1026 #size-cells = <0>;
1028 reg = <0x021a4000 0x4000>;
1036 #size-cells = <0>;
1038 reg = <0x021a8000 0x4000>;
1046 reg = <0x021b0000 0x4000>;
1052 reg = <0x021b4000 0x4000>;
1063 fsl,stop-mode = <&gpr 0x10 4>;
1071 reg = <0x021b8000 0x4000>;
1082 reg = <0x021bc000 0x4000>;
1086 reg = <0x10 4>;
1090 reg = <0x38 4>;
1094 reg = <0x20 4>;
1100 reg = <0x021d4000 0x4000>;
1104 <&clks 0>, <&clks 0>;
1107 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1113 reg = <0x021d8000 0x4000>;
1119 reg = <0x021dc000 0x4000>;
1123 <&clks 0>, <&clks 0>;
1126 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1132 #size-cells = <0>;
1134 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1145 #size-cells = <0>;
1147 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1159 reg = <0x021e8000 0x4000>;
1164 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1172 reg = <0x021ec000 0x4000>;
1177 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1185 reg = <0x021f0000 0x4000>;
1190 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1198 reg = <0x021f4000 0x4000>;
1203 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1210 #size-cells = <0>;
1212 reg = <0x021f8000 0x4000>;
1223 reg = <0x02200000 0x100000>;
1230 reg = <0x02240000 0x40000>;
1234 reg = <0x02214000 0x4000>;
1245 reg = <0x02218000 0x4000>;
1254 reg = <0x0221c000 0x4000>;
1265 reg = <0x02220000 0x4000>;
1277 reg = <0x02224000 0x4000>;
1288 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1300 reg = <0x02280000 0x4000>;
1311 reg = <0x02284000 0x4000>;
1322 reg = <0x02288000 0x4000>;
1330 #size-cells = <0>;
1332 reg = <0x0228c000 0x4000>;
1343 reg = <0x022a0000 0x4000>;
1348 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1355 reg = <0x022a4000 0x4000>;
1365 reg = <0x022a8000 0x4000>;
1375 reg = <0x022ac000 0x4000>;
1385 reg = <0x0022b0000 0x4000>;
1396 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1401 bus-range = <0x00 0xff>;
1402 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1403 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1408 interrupt-map-mask = <0 0 0 0x7>;
1409 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1410 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1411 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1412 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;