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Lines Matching full:clkc

6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
28 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
30 clocks = <&clkc CLKID_CPUCLK>;
39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
41 clocks = <&clkc CLKID_CPUCLK>;
50 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
52 clocks = <&clkc CLKID_CPUCLK>;
61 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
63 clocks = <&clkc CLKID_CPUCLK>;
201 compatible = "amlogic,meson8-ddr-clkc";
255 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
258 assigned-clocks = <&clkc CLKID_MALI>;
458 clocks = <&clkc CLKID_EFUSE>;
468 clocks = <&clkc CLKID_ETH>;
480 clkc: clock-controller { label
481 compatible = "amlogic,meson8-clkc";
492 clocks = <&clkc CLKID_VPU>;
494 assigned-clocks = <&clkc CLKID_VPU>;
501 clocks = <&clkc CLKID_RNG0>;
506 clocks = <&clkc CLKID_CLK81>;
510 clocks = <&clkc CLKID_CLK81>;
514 clocks = <&clkc CLKID_CLK81>;
536 clocks = <&clkc CLKID_PERIPH>;
549 clocks = <&clkc CLKID_PERIPH>;
568 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
578 <&clkc CLKID_FCLK_DIV4>,
579 <&clkc CLKID_FCLK_DIV3>,
580 <&clkc CLKID_FCLK_DIV5>,
581 <&clkc CLKID_SDHC>;
587 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
592 clocks = <&clkc CLKID_CLK81>;
596 clocks = <&xtal>, <&clkc CLKID_CLK81>;
602 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
608 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
614 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
620 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
626 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
632 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
638 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
645 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;