Lines Matching +full:0 +full:x1b000000
25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
75 #clock-cells = <0>;
82 #clock-cells = <0>;
92 thermal-sensors = <&thermal 0>;
96 threshold: trip-point@0 {
108 cpu_crit: cpu_crit@0 {
128 reg = <0 0x10000000 0 0x1000>;
134 reg = <0 0x10001000 0 0x1000>;
141 reg = <0 0x10003000 0 0x1000>;
148 reg = <0 0x10005000 0 0x1000>;
154 reg = <0 0x10006000 0 0x1000>;
165 reg = <0 0x10007000 0 0x100>;
171 reg = <0 0x10008000 0 0x80>;
179 reg = <0 0x1000b000 0 0x1000>;
192 reg = <0 0x1000c000 0 0x1000>;
206 reg = <0 0x10200100 0 0x1c>;
215 reg = <0 0x10204000 0 0x400>;
221 reg = <0 0x10205000 0 0x1000>;
231 reg = <0 0x10209000 0 0x1000>;
240 reg = <0 0x10211000 0 0x1000>,
241 <0 0x10212000 0 0x2000>,
242 <0 0x10214000 0 0x2000>,
243 <0 0x10216000 0 0x2000>;
248 reg = <0 0x11001000 0 0x1000>;
258 reg = <0 0x11002000 0 0x400>;
268 reg = <0 0x11003000 0 0x400>;
278 reg = <0 0x11004000 0 0x400>;
288 reg = <0 0x11005000 0 0x400>;
298 reg = <0 0x11007000 0 0x70>,
299 <0 0x11000200 0 0x80>;
305 #size-cells = <0>;
312 reg = <0 0x11008000 0 0x70>,
313 <0 0x11000280 0 0x80>;
319 #size-cells = <0>;
326 reg = <0 0x11009000 0 0x70>,
327 <0 0x11000300 0 0x80>;
333 #size-cells = <0>;
340 #size-cells = <0>;
341 reg = <0 0x1100a000 0 0x100>;
351 #thermal-sensor-cells = <0>;
353 reg = <0 0x1100b000 0 0x1000>;
365 reg = <0 0x1100d000 0 0x1000>;
373 #size-cells = <0>;
378 reg = <0 0x1100e000 0 0x1000>;
388 reg = <0 0x11014000 0 0xe0>;
393 #size-cells = <0>;
400 #size-cells = <0>;
401 reg = <0 0x11016000 0 0x100>;
413 #size-cells = <0>;
414 reg = <0 0x11017000 0 0x1000>;
425 reg = <0 0x11220000 0 0x2000>;
511 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
517 reg = <0 0x14000000 0 0x1000>;
523 reg = <0 0x1400a000 0 0x1000>;
532 reg = <0 0x14010000 0 0x1000>;
534 mediatek,larb-id = <0>;
543 reg = <0 0x15000000 0 0x1000>;
549 reg = <0 0x15001000 0 0x1000>;
560 reg = <0 0x15004000 0 0x1000>;
575 reg = <0 0x1500a000 0 0x1000>;
587 reg = <0 0x16000000 0 0x1000>;
593 reg = <0 0x16010000 0 0x1000>;
604 reg = <0 0x1a000000 0 0x1000>;
611 reg = <0 0x1a1c0000 0 0x1000>,
612 <0 0x1a1c4700 0 0x0100>;
625 reg = <0 0x1a1c4000 0 0x0700>;
632 reg = <0 0x1a1c4800 0 0x0100>;
640 reg = <0 0x1a1c4900 0 0x0700>;
650 reg = <0 0x1a240000 0 0x1000>,
651 <0 0x1a244700 0 0x0100>;
664 reg = <0 0x1a244000 0 0x0700>;
671 reg = <0 0x1a244800 0 0x0100>;
679 reg = <0 0x1a244900 0 0x0700>;
690 reg = <0 0x11200000 0 0x1000>;
705 reg = <0 0x11210000 0 0x0800>;
712 reg = <0 0x11210800 0 0x0100>;
722 reg = <0 0x1b000000 0 0x1000>;
729 reg = <0 0x1b100000 0 0x20000>;
747 #size-cells = <0>;
753 reg = <0 0x1c000000 0 0x1000>;