Lines Matching +full:- +full:pinmux
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
7 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
8 #include <dt-bindings/mfd/stm32f7-rcc.h>
12 pinctrl: pin-controller {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&exti>;
18 pins-are-numbered;
21 gpio-controller;
22 #gpio-cells = <2>;
23 interrupt-controller;
24 #interrupt-cells = <2>;
27 st,bank-name = "GPIOA";
31 gpio-controller;
32 #gpio-cells = <2>;
33 interrupt-controller;
34 #interrupt-cells = <2>;
37 st,bank-name = "GPIOB";
41 gpio-controller;
42 #gpio-cells = <2>;
43 interrupt-controller;
44 #interrupt-cells = <2>;
47 st,bank-name = "GPIOC";
51 gpio-controller;
52 #gpio-cells = <2>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
57 st,bank-name = "GPIOD";
61 gpio-controller;
62 #gpio-cells = <2>;
63 interrupt-controller;
64 #interrupt-cells = <2>;
67 st,bank-name = "GPIOE";
71 gpio-controller;
72 #gpio-cells = <2>;
73 interrupt-controller;
74 #interrupt-cells = <2>;
77 st,bank-name = "GPIOF";
81 gpio-controller;
82 #gpio-cells = <2>;
83 interrupt-controller;
84 #interrupt-cells = <2>;
87 st,bank-name = "GPIOG";
91 gpio-controller;
92 #gpio-cells = <2>;
93 interrupt-controller;
94 #interrupt-cells = <2>;
97 st,bank-name = "GPIOH";
101 gpio-controller;
102 #gpio-cells = <2>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
107 st,bank-name = "GPIOI";
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
117 st,bank-name = "GPIOJ";
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <2>;
127 st,bank-name = "GPIOK";
130 cec_pins_a: cec-0 {
132 pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
133 slew-rate = <0>;
134 drive-open-drain;
135 bias-disable;
139 usart1_pins_a: usart1-0 {
141 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
142 bias-disable;
143 drive-push-pull;
144 slew-rate = <0>;
147 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
148 bias-disable;
152 usart1_pins_b: usart1-1 {
154 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
155 bias-disable;
156 drive-push-pull;
157 slew-rate = <0>;
160 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
161 bias-disable;
165 i2c1_pins_b: i2c1-0 {
167 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
169 bias-disable;
170 drive-open-drain;
171 slew-rate = <0>;
175 usbotg_hs_pins_a: usbotg-hs-0 {
177 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
189 bias-disable;
190 drive-push-pull;
191 slew-rate = <2>;
195 usbotg_hs_pins_b: usbotg-hs-1 {
197 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
209 bias-disable;
210 drive-push-pull;
211 slew-rate = <2>;
215 usbotg_fs_pins_a: usbotg-fs-0 {
217 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
220 bias-disable;
221 drive-push-pull;
222 slew-rate = <2>;
226 sdio_pins_a: sdio-pins-a-0 {
228 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
234 drive-push-pull;
235 slew-rate = <2>;
239 sdio_pins_od_a: sdio-pins-od-a-0 {
241 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
246 drive-push-pull;
247 slew-rate = <2>;
251 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
252 drive-open-drain;
253 slew-rate = <2>;
257 sdio_pins_b: sdio-pins-b-0 {
259 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
265 drive-push-pull;
266 slew-rate = <2>;
270 sdio_pins_od_b: sdio-pins-od-b-0 {
272 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
277 drive-push-pull;
278 slew-rate = <2>;
282 pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
283 drive-open-drain;
284 slew-rate = <2>;