Lines Matching full:rcc
45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
145 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
146 clocks = <&rcc I2C1_CK>;
157 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
158 clocks = <&rcc I2C2_CK>;
169 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
170 clocks = <&rcc I2C3_CK>;
177 clocks = <&rcc DAC12_CK>;
203 clocks = <&rcc USART1_CK>;
212 resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
213 clocks = <&rcc SPI1_CK>;
223 resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
224 clocks = <&rcc SPI4_CK>;
234 resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
235 clocks = <&rcc SPI5_CK>;
250 clocks = <&rcc DMA1_CK>;
268 clocks = <&rcc DMA2_CK>;
282 clocks = <&rcc DMA1_CK>;
289 clocks = <&rcc ADC12_CK>;
320 clocks = <&rcc USB1OTG_CK>;
332 clocks = <&rcc USB2OTG_CK>;
341 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
342 clocks = <&rcc LTDC_CK>;
351 clocks = <&rcc MDMA_CK>;
363 clocks = <&rcc SDMMC1_CK>;
365 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
390 resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
391 clocks = <&rcc SPI6_CK>;
402 resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
403 clocks = <&rcc I2C4_CK>;
412 clocks = <&rcc LPTIM2_CK>;
439 clocks = <&rcc LPTIM3_CK>;
459 clocks = <&rcc LPTIM4_CK>;
473 clocks = <&rcc LPTIM5_CK>;
487 clocks = <&rcc VREF_CK>;
496 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
498 assigned-clocks = <&rcc RTC_CK>;
499 assigned-clock-parents = <&rcc LSE_CK>;
506 rcc: reset-clock-controller@58024400 { label
507 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
524 clocks = <&rcc ADC3_CK>;
549 clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;