Lines Matching full:ccu
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
106 clocks = <&ccu CLK_CPU>;
122 clocks = <&ccu CLK_CPU>;
138 clocks = <&ccu CLK_CPU>;
154 clocks = <&ccu CLK_CPU>;
279 clocks = <&ccu CLK_AHB1_DMA>;
280 resets = <&ccu RST_AHB1_DMA>;
289 resets = <&ccu RST_AHB1_LCD0>,
290 <&ccu RST_AHB1_LVDS>;
293 clocks = <&ccu CLK_AHB1_LCD0>,
294 <&ccu CLK_LCD0_CH0>,
295 <&ccu CLK_LCD0_CH1>,
296 <&ccu 15>;
343 resets = <&ccu RST_AHB1_LCD1>,
344 <&ccu RST_AHB1_LVDS>;
346 clocks = <&ccu CLK_AHB1_LCD1>,
347 <&ccu CLK_LCD1_CH0>,
348 <&ccu CLK_LCD1_CH1>,
349 <&ccu 15>;
394 clocks = <&ccu CLK_AHB1_MMC0>,
395 <&ccu CLK_MMC0>,
396 <&ccu CLK_MMC0_OUTPUT>,
397 <&ccu CLK_MMC0_SAMPLE>;
402 resets = <&ccu RST_AHB1_MMC0>;
415 clocks = <&ccu CLK_AHB1_MMC1>,
416 <&ccu CLK_MMC1>,
417 <&ccu CLK_MMC1_OUTPUT>,
418 <&ccu CLK_MMC1_SAMPLE>;
423 resets = <&ccu RST_AHB1_MMC1>;
436 clocks = <&ccu CLK_AHB1_MMC2>,
437 <&ccu CLK_MMC2>,
438 <&ccu CLK_MMC2_OUTPUT>,
439 <&ccu CLK_MMC2_SAMPLE>;
444 resets = <&ccu RST_AHB1_MMC2>;
455 clocks = <&ccu CLK_AHB1_MMC3>,
456 <&ccu CLK_MMC3>,
457 <&ccu CLK_MMC3_OUTPUT>,
458 <&ccu CLK_MMC3_SAMPLE>;
463 resets = <&ccu RST_AHB1_MMC3>;
475 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
476 <&ccu CLK_HDMI_DDC>,
477 <&ccu CLK_PLL_VIDEO0_2X>,
478 <&ccu CLK_PLL_VIDEO1_2X>;
480 resets = <&ccu RST_AHB1_HDMI>;
514 clocks = <&ccu CLK_AHB1_OTG>;
515 resets = <&ccu RST_AHB1_OTG>;
533 clocks = <&ccu CLK_USB_PHY0>,
534 <&ccu CLK_USB_PHY1>,
535 <&ccu CLK_USB_PHY2>;
539 resets = <&ccu RST_USB_PHY0>,
540 <&ccu RST_USB_PHY1>,
541 <&ccu RST_USB_PHY2>;
553 clocks = <&ccu CLK_AHB1_EHCI0>;
554 resets = <&ccu RST_AHB1_EHCI0>;
564 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
565 resets = <&ccu RST_AHB1_OHCI0>;
575 clocks = <&ccu CLK_AHB1_EHCI1>;
576 resets = <&ccu RST_AHB1_EHCI1>;
586 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
587 resets = <&ccu RST_AHB1_OHCI1>;
597 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
598 resets = <&ccu RST_AHB1_OHCI2>;
602 ccu: clock@1c20000 { label
603 compatible = "allwinner,sun6i-a31-ccu";
618 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
768 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
769 resets = <&ccu RST_APB1_SPDIF>;
781 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
782 resets = <&ccu RST_APB1_DAUDIO0>;
794 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
795 resets = <&ccu RST_APB1_DAUDIO1>;
822 clocks = <&ccu CLK_APB2_UART0>;
823 resets = <&ccu RST_APB2_UART0>;
835 clocks = <&ccu CLK_APB2_UART1>;
836 resets = <&ccu RST_APB2_UART1>;
848 clocks = <&ccu CLK_APB2_UART2>;
849 resets = <&ccu RST_APB2_UART2>;
861 clocks = <&ccu CLK_APB2_UART3>;
862 resets = <&ccu RST_APB2_UART3>;
874 clocks = <&ccu CLK_APB2_UART4>;
875 resets = <&ccu RST_APB2_UART4>;
887 clocks = <&ccu CLK_APB2_UART5>;
888 resets = <&ccu RST_APB2_UART5>;
898 clocks = <&ccu CLK_APB2_I2C0>;
899 resets = <&ccu RST_APB2_I2C0>;
911 clocks = <&ccu CLK_APB2_I2C1>;
912 resets = <&ccu RST_APB2_I2C1>;
924 clocks = <&ccu CLK_APB2_I2C2>;
925 resets = <&ccu RST_APB2_I2C2>;
937 clocks = <&ccu CLK_APB2_I2C3>;
938 resets = <&ccu RST_APB2_I2C3>;
949 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
951 resets = <&ccu RST_AHB1_EMAC>;
970 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
972 resets = <&ccu RST_AHB1_SS>;
981 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
983 resets = <&ccu RST_APB1_CODEC>;
997 clocks = <&ccu CLK_AHB1_HSTIMER>;
998 resets = <&ccu RST_AHB1_HSTIMER>;
1005 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1009 resets = <&ccu RST_AHB1_SPI0>;
1019 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1023 resets = <&ccu RST_AHB1_SPI1>;
1033 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1037 resets = <&ccu RST_AHB1_SPI2>;
1047 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1051 resets = <&ccu RST_AHB1_SPI3>;
1072 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1073 <&ccu CLK_DRAM_FE0>;
1076 resets = <&ccu RST_AHB1_FE0>;
1104 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1105 <&ccu CLK_DRAM_FE1>;
1108 resets = <&ccu RST_AHB1_FE1>;
1136 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1137 <&ccu CLK_DRAM_BE1>;
1140 resets = <&ccu RST_AHB1_BE1>;
1179 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1180 <&ccu CLK_DRAM_DRC1>;
1183 resets = <&ccu RST_AHB1_DRC1>;
1222 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1223 <&ccu CLK_DRAM_BE0>;
1226 resets = <&ccu RST_AHB1_BE0>;
1262 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1263 <&ccu CLK_DRAM_DRC0>;
1266 resets = <&ccu RST_AHB1_DRC0>;
1324 <&ccu CLK_PLL_PERIPH>,
1325 <&ccu CLK_PLL_PERIPH>;